TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 547

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.4.3.7. Interrupt Enable Register (Int_En)
Hardware resets initialize the Interrupt Enable Register to 0x0000_0000. Software resets do not change the register
contents.
The Interrupt Enable Register controls whether to issue an interrupt in response to errors detected by the DMA engine or
in response to some other conditions.
The Early Notification Enable (EarNotEn) bit is shared by applications that are required to reduce latency. When handling
Early Notification, note that the frame descriptor becomes invalid. Only the first buffer descriptor is valid if an Early
Notification interrupt occurs.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 12
11
10
9
8
7
6
5
4
3
2
1
0
Default
Default
Name
Name
TYPE
TYPE
31
15
Mnemonic
NRAbtEn
TxCtlCmpEn
DmParErrEn
DParDEn
EarNotEn
DParErrEn
SSvsErrEn
RmasAbtEn
RTargAbtEn
STargAbtEn
BLExEn
FDAExEn
RESERVED
30
14
29
13
Field Name
Reserved
Non-recoverable Abort Enable
MAC Control Frame
Transmission Complete Enable
DMA Parity Error Enable
Data Parity Detection Enable
Early Notification Enable
Parity Error Detection Enable
System Error Notification Enable
Master Abort Reception Enable
Target Abort Reception Enable
Target Abort Notification Enable
Buffer List Exhaustion
Notification Enable
Free Descriptor Area Exhaust
Notification Enable
28
12
NRAbt
R/W
Figure 18-39 Interrupt Enable Register
27
11
En
0
TxCtlC
mpEn
R/W
26
10
0
DmPar
ErrEn
R/W
25
9
0
18-55
DParD
RESERVED
R/W
Description
NRAbtEn (Default: 0, R/W)
Enables interrupts when a non-recoverable abort occurs
internally.
TxCtlCmpEn (Default: 0, R/W)
Enables interrupts when transmission of the MAC control frame is
complete.
DmParErrEn (Default: 0, R/W)
Enables interrupts if a parity error is detected when reading or
writing from/to DMA-internal RAM.
DParDEn (Default: 0, R/W)
Enables interrupts when bit 8 of the PCI Status Register is set.
EarNotEn (Default: 0, R/W)
When receiving a reception packet, issues an interrupt not only
when reaching the tail of a packet, but also issues an interrupt
when writing the first buffer or its descriptor.
DParErrEn (Default: 0, R/W)
Enables interrupts if a parity error is detected during PCI Bus
transfer while the Ethernet Controller is accessing the Bus
Master.
SSvsErrEn (Default: 0, R/W)
Enables interrupts if the Ethernet Controller signals a system
error.
RmasAbtEn (Default: 0, R/W)
Enables interrupts if a Master Abort is received while the Ethernet
Controller is operating as the Target.
RTargAbtEn (Default: 0, R/W)
Enables interrupts if a Target Abort is received while the Ethernet
Controller is operating as the Target.
STargAbtEn (Default: 0, R/W)
Enables interrupts if a Target Abort is issued while the Ethernet
Controller is operating as the Target.
BLExEn (Default: 0, R/W)
Enables interrupts when the buffer list is completely used up. In
other words, enables interrupts when the Ethernet Controller
encounters descriptors owned by the system that still remain in
the buffer list.
FDAExEn (Default: 0, R/W)
Enables interrupts when the free descriptor area is totally used
up. In other words, enables interrupts when the Ethernet
Controller encounters blocks owned by the system that still
remain in the FDA.
24
En
8
0
0x18
EarNot
R/W
En
23
7
0
DParE
rrEn
R/W
22
6
0
SSvsE
R/W
rrEn
21
5
0
AbtEn
Rmas
R/W
20
4
0
Toshiba RISC Processor
RTarg
AbtEn
R/W
19
3
0
STarg
AbtEn
R/W
18
2
0
BLExE
R/W
17
1
n
0
TX4939
FDAEx
R/W
En
16
0
0
18
18

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