TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 552

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
Transmission Control Frame Status Register (TxCtlFrmStat)
The Transmission Control Frame Status Register uses part of the internal RAM, so it is not affected by hardware resets
or software resets.
The Transmission Control Frame Status Register displays via the SdPause bit of the Transmission Control Register the
status when the MAC control frame was transmitted to a remote station.
After transmission ends, the software driver fetches the status from this register. The software can reset this register
before starting transmission of the MAC control frame. The software can use the TxCtlCmpEn bit of the Interrupt Enable
Register to issue an interrupt when transmission of the MAC control frame ends.
For information on the bit fields, see the explanation of the Transmission Status Register (Tx_Stat) in 18.4.5.3
Transmission Control, Status Registers.
Rev. 3.1 November 1, 2005
Bits
31 : 22
21 : 0
Default
Default
Name
Name
TYPE
TYPE
31
15
Mnemonic
Tx_Stat Value
30
14
29
13
Field Name
Reserved
Transmission Control Frame
Status
Figure 18-45 Transmission Control Frame Status Register
28
12
RESERVED
27
11
26
10
25
9
18-60
Tx_Stat Value
Description
Tx_Stat (Default: -, R/W)
The Transmission Control Frame Status Register displays via the
SdPause bit of the Transmission Control Register the status from
when the MAC control frame was transmitted to a remote station.
24
8
R/W
-
23
7
0x38
22
6
21
5
20
4
Toshiba RISC Processor
Tx_Stat Value
19
3
R/W
-
18
2
17
1
TX4939
16
0
18
18