TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 556

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
Transmission Status Register (Tx_Stat) 0x4C
Software resets initialize the Transmission Status Register to 0x00_0000. Also, this register is cleared at the beginning of
each transmission packet.
The Transmission Status flag is set each time the applicable event occurs. Also, an interrupt occurs if the corresponding
bit of the Transmission Control Register is set.
The lower 5 bits of the Transmission Status Register indicate the collision count of the packet. In other words, when
ExColl=1, TxColl becomes 0. If TxColl is not 0, then ExColl=0.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3 : 0
Default
Default
Name
Name
TYPE
TYPE
Mneminc
TxPAUSE
TxMACC
TxVLAN
TxBCast
TxMCast
SQErr
TxHalted
Comp
TxPar
LateColl
ExDefer
Under
IntTx
Paused
TxDefer
ExColl
TxColl
TxHalted Comp TxPar LateColl Reserved Reserved ExDefer Under IntTx
31
15
R
0
30
14
R
0
Field Name
Reserved
Pause Packet
Communication
MAC Control Packet
Transmission
VLAN Tag Packet
Transmission
Broadcast
Transmission
Multicast
Transmission
Signal Quality Error
Transmission Halted
Complete
Transmission Parity
Error
Late Collision
Reserved
Reserved
Excessive Deferral
Underrun
Transmission Interrupt IntTx (Default: 0, R)
Transmitter Paused
Transmission
Deferred
Excessive Collisions
Transmission Collision
Count
29
13
R
0
28
12
R
0
Figure 18-49 Transmission Status Register (2/2)
RESERVED
27
11
26
10
Description
TxPAUSE (Default: 0, R)
This bit is set when MAC transmits a MAC control Pause packet.
TxMACC (Default: 0, R)
This bit is set when MAC transmits a MAC control packet.
TxVLAN (Default: 0, R)
This bit is set when MAC transmits a VLAN tag packet.
TxBCast (Default: 0, R)
This bit is set when MAC transmits a broadcast packet.
TxMCast (Default: 0, R)
This bit is set when MAC transmits a multicast packet.
SQErr (Default: 0, R)
Indicates that the Heartbeat signal could not be monitored at the end of a
transmission.
TxHalted (Default: 0, R)
Halts transmission by either clearing the TxEn bit of the Transmission Control
Register or setting the HaltImm bit of the MAC Control Register.
Comp (Default: 0, R)
Indicates that MAC either transmitted or destroyed one packet.
TxPar (Default: 0, R)
Indicates that a parity error was detected in MAC Transmission FIFO.
LateColl (Default: 0, R)
Indicates that 512-bit late time (64-Byte time) or more elapsed before a collision
occurred.
ExDefer (Default: 0, R)
Indicates that MAC deferred transmission for more than MAX_DEFERRAL.
Under (Default: 0 ,R)
Indicates that MAC Transmission FIFO became empty during transmission.
This bit is set when interrupt conditions specified by the Transmission Control
Register are met in a packet transmission.
Paused (Default: 0, R)
This bit is set if transmission is paused after the current packet ends.
TxDefer (Default: 0, R)
Indicates that a packet was kept waiting due to transmission delay.
ExColl (Default: 0, R)
This bit is set if collisions occur 16 times in the same packet. Instead of
transmitting that packet, processing of the next packet transmission starts.
TxColl (Default: 0, R)
Number of collisions that occurred when transmitting one packet.
25
R
9
0
18-64
24
R
8
0
23
R
7
0
Paused
22
R
6
0
TxPAUSE TxMACC TxVLAN TxBCast TxMCast SQErr
TxDefer ExColl
21
R
R
0
5
0
20
R
R
0
4
0
Toshiba RISC Processor
19
R
R
0
3
0
18
R
R
0
2
0
TxColl
17
R
R
0
1
0
TX4939
16
R
R
0
0
0
18
18

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