TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 557

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
The MAX_DEFERRAL time is 0.24288 ms for 100 Mbps and 2.42880 ms for 10 Mbps. If the TxMCast bit (bit 17) and the
TxBCast bit (bit 18) are both "0", they indicate that a unicast packet was transmitted.
18.4.5.4. Reception Control, Status Register
Reception Control Register (Rx_Ctl)
1
MAC frames and packets.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Default
Default
Name
TYPE
Name Reserved EnGood EnRxPar EnLenErr
TYPE
The above frame length does not include a preamble and a Start Frame Delimiter (SFD). For details, see 18.3.8.1 Format of
Mnemonic
EnGood
EnRxPar
EnLenErr
EnLongErr
EnOver
EnCRCErr
EnAlign
IgnoreLen
IgnoreCRC
PassCtl
StripCRC
ShortEn
LongEn
RxHalt
R/W
31
15
0
R/W
30
14
0
R/W
Field Name
Reserved
Transmission Enable
Enable Reception
Parity
Enable Frame Length
Errors
Enable Long Errors
Enable Overflows
Enable CRC Errors
Enable Alignment
Ignore Frame Length
Ignore CRC Value
Pass MAC Control
Frame
Strip CRC Value
Enable Short
Long Enable
Reception Halt
Request
13
29
0
R/W
28
12
0
Figure 18-50 Reception Control Register
Table 18-11 Reception Control Register
EnLong
R/W
Err
27
11
0
0x50
EnOver
Description
EnGood (Default: 0, R/W)
Issues an interrupt if a packet is received without any error.
EnRxPar (Default: 0, R/W)
Issues an interrupt if a parity error is detected in the MAC Reception FIFO.
EnLenErr(Default: 0, R/W)
Issues an interrupt if a Frame Length error is detected.
EnLongErr (Default: 0, R/W)
If the LongEn bit is not set, an interrupt is issued when a frame longer than 1518
Bytes (1522 Bytes for VLAN) is received.
EnOver (Default: 0, R/W)
Issues an interrupt if the MAC Reception FIFO becomes full when receiving a
packet.
EnCRCErr (Default: 0, R/W)
Issues an interrupt either when CRC receives an invalid packet or PHY asserts
Rx_er while receiving a packet.
EnAlign (Default: 0, R/W)
Issues an interrupt if CRC receives an invalid packet with a length that is not a
multiple of 8.
Does not check the frame length.
IgnoreCRC (Default: 0, R/W)
Does not check CRC.
PassCtl (Default: 0, R/W)
Passes a received MAC control frame to the system.
StripCRC (Default: 0, R/W)
Checks CRC, but removes it from the message.
ShortEn (Default: 0, R/W)
Enables the reception of frames shorter than 64 Bytes. 1
LongEn (Default: 0, R/W)
Enables the reception of frames longer than 1518 Bytes (1522 Bytes in the case
of VLAN). 1
RxHalt (Default: 0, R/W)
Halts reception after the current packet ends regardless of the packet type.
R/W
IgnoreLen (Default: 0, R/W)
26
10
0
EnCRC
R/W
Err
25
18-65
9
0
RESERVED
EnAlign IgnoreLen
R/W
24
8
0
R/W
23
7
0
Ignore
CRC
R/W
22
6
0
PassCtl
R/W
21
5
0
Toshiba RISC Processor
CRC
R/W
Strip
20
4
0
ShortEn LongEn RxHalt RxEn
R/W
19
3
0
R/W
18
2
0
R/W
17
1
0
TX4939
R/W
16
0
0
18
18