TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 559

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
Reception Status Register (Rx_Stat)
1 The above frame length does not include a preamble and a Start Frame Delimiter (SFD). For details, see 18.3.8.1
Rev. 3.1 November 1, 2005
Bit(s)
31 : 30
29 : 25
24 : 21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
Format of MAC frames and packets.
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
ARCEnt
ARCStatus
RxPause
RxVLAN
RxBCast
RxMCast
RxHalted
Good
RxPar
TypePkt
LongErr
Overflow
CRCErr
AlignErr
RxHalted Good RxPar TypePkt LongErr Overflow CRCErr AlignErr Reserved IntRx CtlRecd InLenErr
RESERVED
31
15
R
1
30
14
R
0
Field Name
Reserved
ARC Entry
ARC Status
PAUSE Packet
Reception
VLAN Tagged Packet
Reception
Broadcast Reception
Multicast Reception
Reserved
Reception Halted
Normal Reception
Reception Parity Error RxPar (Default: 0, R)
Type Packet
Long Error
Overflow
CRC Error
Alignment Error
Reserved
29
13
R
0
28
12
R
0
ARCEnt
Figure 18-51 Reception Status Register
0x1f
Table 18-12 Reception Status Register
27
11
R
R
0
0x54
26
10
Description
ARCEnt (Default: 0x1F, R)
This field stores the ARC entry index if the address matches. If the address does
not match, all bits become "1".
ARCStatus (Default: 0, R)
Denotes ARC operation (see the following encoding).
RxPause (Default: 0, R)
This bit is set when the reception packet is a MAC control PAUSE packet.
RxVLAN (Default: 0, R)
This bit is set when the reception packet is a VLAN tagged packet.
RxBCast (Default: 0, R)
This bit is set when the reception packet is a broadcast packet.
RxMCast (Default: 0, R)
This bit is set when the reception packet is a multicast packet.
RxHalted (Default: 1, R)
This bit indicates that reception was halted either when the RxEn bit of the
Reception Control Register was cleared or the HaltImm bit of the MAC Control
Register was set.
Good (Default: 0, R)
Indicates that a packet was received without any errors occurring.
Indicates that a parity error was detected in the MAC Reception FIFO.
TypePkt (Default: 0, R)
The value of the Frame Length field is greater than 1500 (no frame length check
is performed). The software can use this bit to check the Protocol Type field.
LongErr (Default: 0, R)
Indicates that a frame longer than 1518 Bytes (1522 Bytes for VLAN)1 was
received. However, if the LongEn bit of the Reception Control Register is set, this
bit is not set.
Overflow (Default: 0, R)
Indicates that the MAC Reception FIFO is full and a reception byte is missing.
CRCErr (Default: 0, R)
Indicates that either the CRC value at the end of the packet does not match the
calculated value or PHY asserted Rx_er while receiving a packet.
AlignErr (Default: 0, R)
Indicates that the frame length is not an 8-bit multiple and that CRC is invalid.
R
0
25
R
9
0
18-67
24
R
8
0
ARCStatus
23
7
0x0
R
22
R
6
0
21
R
5
0
RxPause RxVLAN RxBCast RxMCast Reserved
20
R
R
0
4
0
Toshiba RISC Processor
19
R
0
3
18
Reserved
R
0
2
17
R
0
1
TX4939
16
R
0
0
18
18