TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 560

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
Software resets initialize the Reception Status Register to 0x3E00_8000. This register is also cleared at the beginning of
each reception packet.
The Reception Status flag is set each time the applicable event occurs. Once the Reception Status flag is set, it remains
set until the next packet is reached. When the corresponding bit of the Reception Control Register is set, an interrupt is
issued.
The CtlRecd bit is set when the packet type is 0x8808 and the ARC recognizes an address. If both the RxMCast bit (bit
17) and the RxBCast bit (bit 18) are "0", they indicate that a unicast packet was received.
The ARCStatus field is encoded as follows below.
Rev. 3.1 November 1, 2005
Bit(s)
6
5
4
3 : 0
Mnemonic
IntRx
CtlRecd
InLenErr
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1xx1:
1010:
1100:
1110:
Note
Toss. MAC control frame received. PassCtl=0.
Toss. The packet length is less than the minimum packet length,
but is 6 Bytes or more. Keep if that is not the case.
Toss. Matches ARC. NOT filtering.
Reserved
Toss. External CAM bit. NOT filtering.
Reserved
Toss. Address does not match. No external CAM. Compare
disable. AND filtering.
Toss. State in which the packet length is too short, the ARC
result is Invalid, and the ShortEn bit is not set.
Keep. Broadcast, multicast, or unicast accepting is enabled and
the address matches.
Reserved
Keep. ARC matches. AND filtering.
Keep. External CAM bit. AND filtering.
Keep. ARC does not match. AND filtering.
The minimum packet length is 64 Bytes if ShortEn is not
asserted, or is 14 Bytes if ShortEn is asserted.
Racing occurs between the internal ARC and external CAM.
There are cases where the first signal to notify a hit blocks the
other signal that notifies a hit and the ARC's Entry Status bit
changes.
Field Name
Reception Interrupt
Control Frame
Received
In Range Frame
Length Error
Reserved
Table 18-12 Reception Status Register
Description
IntRx (Default: 0, R)
This bit is set when interrupt conditions are met due to the reception of a packet.
If the EnGood bit of the Reception Control Register is set, notification is also sent
for packets received without any errors.
Note:
packet when the EnGood bit or EnCRCErr bit of the Reception Control
Register is set, this IntRx bit is also set if the Good or CRCErr bit of the
Reception Status Register is set. In this case however, no interrupt
notification is sent and the IntMacRx bit of the Int_Src Register is not set.
CtlRecd (Default: 0, R)
This bit is set if the ARC recognizes an address when the received packet is the
MAC control frame (type=0x8808).
InLenErr (Default: 0, R)
If the value of the Frame Length field is 46 or less, this bit is set when the
reception packet size is not 64 Bytes. Also, if the value of the Frame Length field
is between 47 and 1500, this bit is set when the reception packet size is not the
value of the Frame Length field + 18 (14 when in the Strip CRC mode).
18-68
If the Address Recognition Circuit (ARC) destroys a received
Toshiba RISC Processor
TX4939
18
18