TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 566

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.5.7. Missed Error Count Register (Miss_Cnt)
Hardware resets initialize the Missed Error Count Register to 0x0000_0000. Software resets do not change the contents
of this register.
The Missed Error Count Register displays the number of packets destroyed by various error types. This register provides
the information required for station management along with the status information of the transmission/reception packet.
Performing read access to the Missed Error Count Register clears it. Therefore, the software is responsible for increasing
the bit count and retaining the precise total error count.
The MissRoll bit of the MAC Control Register is set when the Missed Error Count Register rolls over from 0x7FFF to
0x8000. Also, in this case an interrupt occurs if the EnMissRoll bit is set.
To generate interrupts more frequently from the Station Management software, you can set the Missed Error Count
Register to a value that is close to the final count value of 0x7FFF. For example, if you set this register to 0x7F00, an
interrupt occurs when errors have occurred 256 times.
0x74 through 0x78 is reserved to maintain compatibility with previous Toshiba products.
Rev. 3.1 November 1, 2005
Bits
31 : 16
15 : 0
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
Miss_Cnt
31
15
30
14
Field Name
Reserved
Missed Error Count
29
13
28
12
Figure 18-57 Missed Error Count Register
27
11
26
10
Description
Miss_Cnt (Default: 0x0000, R/W)
This register counts the number of valid packets MAC refused due to MAC
Reception FIFO overflow, parity error, or the clearing of the Reception Enable bit
(RxEn). This count does not include the packets refused by ARC.
25
9
18-74
RESERVED
24
Miss_Cnt
8
0x0000
R/W
23
7
0x7C
22
6
21
5
20
4
Toshiba RISC Processor
19
3
18
2
17
1
TX4939
16
0
18
18