TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 569

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
19.3. Detailed Explanation
TX4939 has dedicated ports for SIO0 and SIO1 while sharing SIO2 and SIO3 ports with SPI and GPIO. Depending on the
requirement, SIO2 and SIO3 ports can be activated by writing to Pin Configuration Register (PCFG) described in Chapter 7.
Configuration Registers after boot up. TX4939 also allows SIO0 hardware flow control signals based on PCFG. Activation
of SIO0 hardware flow control signals, SIO2 and SIO3 ports is independent of Product Mode Selection (see Chapter 4. Boot
Configuration, Table 4-1 Boot Configuration Details, for Product Mode Selection). Table 19-1 gives PCFG settings that are
needed to activate SIO2 and SIO3 and SIO0 CTSB/RSTB (hardware flow control signals).
The following sections describe a single SIO channel that is also applicable to the remaining 3 SIO channels unless
otherwise specified.
19.3.1. Overview
During reception, serial data that are input as an RXD signal from an external source are converted into parallel data, then
are stored in the Receive FIFO buffer. Parallel data stored in the FIFO buffer are fetched by either CPU or DMA transfer.
During transmission, parallel data written to the Transmit FIFO buffer by CPU or DMA transfer are converted into serial data,
then are output as a TXD signal.
19.3.2. Data Format
The TX4939 SIO can use the following data formats.
Figure 19-2 illustrates the data frame when making each setting.
Rev. 3.1 November 1, 2005
Note:
PCFG[63:61,57] defaults to GPIO interface after boot up. The behavior of unusable SIO
channels as given in Table 19-1 is not defined when unusable SIO channels are accessed
through IMBUS.
PCFG[63:61,57]
4’bxx0x
4’b1x11
4’b0010
4’b0011
4’b0110
4’b0111
4’b1x10
Data Length
Stop Bit
Parity Bit
Parity Format
Start Bit
Table 19-1 Usable SIO channels based on PCFG settings
Active Interface
SPI
GPIO
SIO
SIO0/GPIO
SIO2/SIO3
SIO2/GPIO
GPIO, SIO3
: 8/7 bits
: 1/2 bits
: Yes/No
: Even/Odd
: Fixed to 1 bit
SIO0 (CTSB/RTSB) SIO2
Unusable
Unusable
Usable
Usable
Unusable
Unusable
Unusable
19-3
Unusable
Unusable
Unusable
Unusable
Usable
Usable
Unusable
Toshiba RISC Processor
SIO3
Unusable
Unusable
Usable
Unusable
Usable
Unusable
Usable
TX4939
19
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