TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 573

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
Table 19-4 gives example divide value settings and percentage error from targeted baud rates when SCLK1 is used to
generate SIOCLK (Figure 19-3). Exact target baud rates cannot be achieved when using SCLK1 to generate SIOCLK.
19.3.4. Data Reception
When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set to “0”, reception operation
starts after the RXD signal start bit is detected. Start bits are detected when the RXD signal transitions from the High state
to the Low state. Therefore, the RXD signal is not interpreted as a start bit if it is Low when the Serial Data Reception Disable
bit is set to “0”.
The received data are stored in the Receive FIFO. The Reception Data Full bit (RDIS) of the DMA/Interrupt Status Register
(SIDISRn) is set if the byte count of the stored reception data exceeds the value set by the Receive FIFO Request Trigger
Level field (RDIL) of the FIFO Control Register (SIFCRn).
An interrupt is signaled when the Reception Data Interrupt Enable bit (RIE) of the DMA/Interrupt Control Register (SIDICRn)
is set. The received data can be read from the Receive FIFO Data Register (SIRFIFOn).
In addition, DMA transfer is initiated when the Reception Data DMA Enable bit (RDE) of the DMA/Interrupt Control Register
(SIDICRn) is set.
19.3.5. Data Transmission
Data stored in the Transmission Data FIFO are transmitted when the Serial Data Transmission Disable bit (TSDE) of the
Flow Control Register (SIFLCRn) is set to “0”.
If the available space in the Transmit FIFO is greater than the byte count set by the Transmit FIFO Request Trigger Level
(TDIL) of the Control Register (SIFCRn), the transmission data empty bit (TDIS) of the DMA/Interrupt Status Register
(SIDISRn) is set.
An interrupt is signaled when the Transmission Data Interrupt Enable bit (TIE) of the DMA/Interrupt Control Register
(SIDICRn) is set.
In addition, DMA transfer is initiated when the Transmission Data DMA Enable bit (TDE) of the DMA/Interrupt Control
Register (SIDICRn) is set.
Rev. 3.1 November 1, 2005
SCLK1 = 14.7465
(Note 1)
Note 1:
Note 2:
Table 19-4 Example Divide Value Settings when using SCLK1 (and error [%] from target baud rate value)
fc [MHz]
SCLK1 (baud rate clock) generation information can be obtained from Chapter 5. Clock
Generators
The baud rate generator circuit (Figure 19-3) is bypassed and SIOCLK is sourced by SCLK1
when SILCR.SCS is set to 3’b100.
Target
Bps
230400
460800
921600
115200
14400
28800
57600
1200
2400
4800
9600
300
600
generator (Note 2)
Bypass baud rate
Note 2 (-0.006%)
192(-0.006%)
96(-0.006%)
48(-0.006%)
32(-0.006%)
16(-0.006%)
8(-0.006%)
4(-0.006%)
2(-0.006%)
1(-0.006%)
19-7
Prescalar Value (SIBGR.BCLK) and Divide Value (SIBGR.BRD)
2
192(-0.006%)
96(-0.006%)
48(-0.006%)
24(-0.006%)
12(-0.006%)
8(-0.006%)
4(-0.006%)
2(-0.006%)
1(-0.006%)
8
Toshiba RISC Processor
96(-0.006%)
48(-0.006%)
24(-0.006%)
12(-0.006%)
6(-0.006%)
3(-0.006%)
2(-0.006%)
1(-0.006%)
32
24(-0.006%)
12(-0.006%)
6(-0.006%)
3(-0.006%)
128
TX4939
19
19