TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 574

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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SIO
19.3.6. DMA Transfer
The four SIO channels share two DMA channels, one for reception and transmission respectively. In TX4939, only one SIO
channel can make use of DMA operations at a time. The SIO channel that is to use DMA operations can be selected by
writing to Chip Configuration Register (CCFG) described in Chapter 7. Chip Configuration. The DMA Request Select field
(INTDMA[7:0]) of the Pin Configuration Register (PCFG) can be used to allocate DMA channels for the reception and
transmission channel in the following manner,
Set the DMA Channel Control Register of the DMA Controller as described below.
In the case of transmission channels, the address of the Transmit FIFO Register (SITFIFOn) is set in the DMAC Destination
Address Register (DMDARn). In the case of reception channels, the address of the Receive FIFO Register (SIRFIFOn) is
set in the DMAC Source Address Register (DMSARn). Please set the addresses specified in “19.4.8 Transmit FIFO
Register” and “19.4.9 Receive FIFO Register” since the set address differs depending on the Endian mode.
19.3.7. Flow Control
This section applies to SIO0 channel only.
SIO0 supports hardware flow control that uses the RTS*/CTS* signal.
The CTS* (Clear to Send) input signal indicates that data can be received from the reception side when it is Low. Setting the
Transmission Enable Select bit (TES) of the Flow Control Register (SIFLCRn) makes transmission flow control that uses the
CTS* signal more effective.
It is also possible to generate status change interrupts by changing the state of the CTS* signal. The conditions in which
interrupts are generated can be selected by the CTSS Active Condition field of the DMA/Interrupt Control Register
(SIDICRn).
Setting the RTS* (Request to Send) output signal to High requests the transmission side to pause transmission.
Transmission resumes when the reception side becomes ready and the RTS* signal is set to Low.
Setting the Reception Enable Select bit (RCS) of the flow Control Register (SIFLCRn) makes reception flow control that
uses the RTS* signal more effective. The RTS* signal pin status becomes High when data of the byte count set by the RTS
Active Trigger Level field (RTSTL) of the Flow Control Register (SIFLCRn) accumulates in the Receive FIFO. The RTS*
signal can also be made High by setting the RTS Software Control bit (RTSSC) of the Flow Control Register (SIFLCRn).
Setting this bit requests the transmission side to pause transmission.
19.3.8. Reception Data Status
Status data such as the following is also stored in the Receive FIFO.
Rev. 3.1 November 1, 2005
SIO Channel 0 Reception
SIO Channel 0 Transmission
DMA Request Polarity
DMA Acknowledge Polarity
Request Detection
Transfer Size
Transfer Address Mode
Overrun error
An overrun error is generated if all 16-stage Receive FIFO buffers become full and more data is transferred to the
Reception Read buffer. When this occurs, the Overrun Status bit is set by the last stage of the Receive FIFO.
Parity error
A parity error is generated when a parity error is detected in the reception data.
Framing error
A framing error is generated when “0” is detected at the first stop bit of the reception data.
Break reception
A break is detected when a framing error occurs in the reception data and all data in a single frame are “0”. When
DMA Channel 2
DMA Channel 3.
1 Byte
Dual
Low Active
Low Active
Level Detection
19-8
DMCCRn.ACKPOL = 0
DMCCRn.REQPOL = 0
DMCCRn.EGREQ = 0
DMCCRn.XFSZ = 000b
DMCCRn.SNGAD = 0
Toshiba RISC Processor
TX4939
19
19

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