TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 577

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
19.3.12. Multi-Controller System
The Multi-Controller System consists of one Master Controller, and multiple Slave Controllers as shown below in Figure
19-5.
In the case of the Multi-Controller System, the Master Controller transmits an address (ID) frame to all Slave Controllers,
then transmits and receives data with the selected Slave Controller. Slave Controllers that were not selected will ignore this
data.
Data frames whose data frame Wake Up bits (WUB) are “1” are handled as address (ID) frames. Data frames whose Wake
Up bit (WUB) is “0” are handled as data frames.
The data transfer procedure for the Multi-Controller System is as follows.
Rev. 3.1 November 1, 2005
(1)
(2)
(3)
(4)
(5)
(6)
Note: Break signaling cannot be done by TX4939 as a slave in a Multi-Controller system”
The Master and Slave Controllers set the Mode field (UMODE) of the Line Control Register (SILCR)
to “10” or “11” to set the Multi-Controller System mode. Also, the Slave Controller sets the open drain
enable bit (UODE) of the Line Control Register (SILCR), setting the TXD output signal to open drain
output.
The Slave Controller sets the Reception Wake Up bit (RWUB) of the Line Control Register (SILCR),
making it possible to receive address (ID) frames from the Master Controller.
The Master Controller sets the Transmission Wake Up bit (TWUB) of the Line Control Register
(SILCR), and transmits the address (ID) of the selected Slave Controller. This causes the address
(ID) frame to be transmitted. The Reception after Address Transmission Wake Up bit (RWUB) is
cleared, enabling reception of data frames.
Since the Reception Wake Up bit (RWUB) is set, the Slave Controller generates an interrupt to the
CPU by receiving an address (ID) frame. The CPU compares its own address (ID) and the received
data together. If they do not match, the Reception Wake Up bit (RWUB) is cleared, making data frame
reception possible.
The Master Controller and the selected Slave Controller clear the Transmission Wake Up bit (TWUB)
of the Line Control Register (SILCR), then set the mode that transmits data frames.
Transmit/Receive data between the Master Controller and the selected Slave Controller. Then, Slave
Controllers that were not selected ignore data frames since the Reception Wake Up bit (RWUB) is still
set.
Figure 19-5 Example Configuration of Multi-Controller System
Slave #1
Master
RXD
RXD
TXD
TXD
19-11
Slave #2
RXD
TXD
Slave #3
RXD
TXD
Toshiba RISC Processor
TX4939
19
19