TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 590

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
19.4.8. Transmit FIFO Register 0,1,2,3
When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address
Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller.
Little Endian: 0xF31C (Ch.0), 0xF35C (Ch.1), 0xF39C (Ch.2), 0xF3DC (Ch.3)
Big Endian:
Rev. 3.1 November 1, 2005
Bit
31:8
7:0
31
15
Mnemonic
TxD
(SITFIFO0, SITFIFO1, SITFIFO2, SITFIFO3)
Channel
SIO0
SIO1
SIO2
SIO3
0xF31F (Ch.0), 0xF35F (Ch.1), 0xF39F (Ch.2), 0xF3DF (Ch.3)
Field Name
Reserved
Transmission
Data
Table 19-20 Address offsets for Transmit FIFO Register in the TX4939
Reserved
Address Offset
0xF31C
0xF41C
0xF39C
0xF49C
Description
Transmit Data
Data written to this register are written to the Transmit FIFO.
Figure 19-13 Transmit FIFO Register
Table 19-21 Transmit FIFO Register
Mnemonic
SITFIFO0
SITFIFO1
SITFIFO2
SITFIFO3
Reserved
8
19-24
7
Register Name
Transmit Fifo Register 0
Transmit Fifo Register 1
Transmit Fifo Register 2
Transmit Fifo Register 3
TxD
W
⎯
Toshiba RISC Processor
16
0
: Initial value
: Initial value
Read/Write
⎯
W
: Type
: Type
TX4939
19
19