TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 595

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SPI
20.3. Operational description
SPI interface ports in TX4939 are shared with SIO2, SIO3 or GPIO ports. The active interface ports are selected by writing
to Pin Configuration Register (PCFG) described in Chapter 7. Configuration Registers after boot up. Table 20-1 gives
PCFG settings that are needed to select SPI ports as the active interface.
The following sections give a detailed description of SPI operations.
20.3.1. Operation modes
The SPI Module has the two following operation modes:
Configuration Mode (OPMODE = “01”):
You can only rewrite the lower byte (bits[7:0]) of SPI Control Register 0 (SPCR0) and all bits of SPI Control Register 1
(SPCR1) when in this mode. Also, the SPSTP bit, Receiver FIFO and Transmitter FIFO are cleared and the SPI Module is
reset when in this mode. Setting this mode forcibly terminates even the transfer of a frame that is currently in progress.
Active Mode (OPMODE = “10”)
The module operates in this mode during normal operation. You can execute transfers when in this mode.
Sleep mode (OPMODE = ‘11’) : In this mode, the SPI module will be set in reset state.
20.3.2. Transmitter/Receiver
The SPI Module is in the Reset state when it is in the Configuration Mode. When in this mode, set the lower byte (bits[7:0])
of SPI Control Register 0 (SPCR0) and SPI Control Register 1 (SPCR1) to the desired value before changing the operation
mode to the Active Mode. The SPI Module can start transferring data once it is in the Active Mode. Transfer starts when data
is written to the SPI Data Register (SPDR).
The data written to the SPI Data Register (SPDR) is sent to the Shift Register, which then outputs the data to the Slave
device. When the data is outputted from the SPIOUT pin, it is simultaneously fetched from the SPIIN pin. When fetching of
the data is complete, the content of the Shift Register is loaded into the Receiver Buffer, the SRRDY bit of the SPI Status
Register (SPSR) becomes “1”, then the Reception Buffer is notified that there is reception data. When the RBSI bit of the SPI
Status Register (SPSR) is set to “1”, an interrupt occurs when the accumulated reception data reaches the level set by the
RXIFL bit of SPI Control Register 0 (SPCR0).
When the content of the Transmitter Buffer is transferred to the Shift Register, the STRDY bit of the SPI Status Register
(SPSR) becomes “1” and notification is sent that the Transmitter Buffer is available for use again. When the TBSI bit of the
SPI Status Register (SPSR) is set to “1”, an interrupt occurs when the accumulated transmission data reaches the level set
by the TXIFL bit of SPI Control Register 0 (SPCR0). Therefore, the software executes the following steps each time it writes
data to the Transmitter Buffer.
In this way, depending on the software used, the SPI Module can continue to seamlessly transmit data as long as the
Transmitter Buffer is in the Run state until the data is shifted out from the Shift Register. If the software cannot keep up with
the transfer rate, the SPI Module waits until the next data is written to the SPI Data Register (SPDR).
Rev. 3.1 November 1, 2005
Note:
(1)
(2)
PCFG[61,57:56] defaults to GPIO interface after boot up. The behavior of SPI is not defined
when SPI is accessed through the IMBUS and SPI interface port is not selected in PCFG.
Check whether the STRDY bit or the TBSI bit is “1”. If neither bit is “1”, wait until one of them becomes “1”.
Write data to the SPI Data Register (SPDR).
Table 20-1 Selecting SPI as the active interface port in TX4939
PCFG[61,57:56]
3’b011
Others
GPIO or SIO2 orSIO3
Active Interface
20-3
SPI
SPI Interface
Unusable
Usable
Toshiba RISC Processor
TX4939
20
20