TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 598

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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SPI
20.3.4.2. SPHA = 1 format
Figure 20-3 shows the transfer format when SPHA is “1”.
When in this format, data is sequentially fetched from the second clock edge after the Idle state. When the SPOL bit is “0”,
the data is fetched from the second falling edge. When the SPOL bit is “1”, the data is fetched from the second rising edge.
When the SPOL bit is “0”, SPICLK is at the Low level during the Idle state. When the SPOL bit is “1”, SPICLK is at the High
level during the Idle state.
20.3.5. Interframe Delay Time Counter
There are cases where it is preferable to shorten the time between data groups. In such cases, the Interframe Delay Time
Counter is used to specify the delay time between data groups. When 16 bits is selected as the data size by SPI Control
Register 1, the delay time is inserted after 16-bit data is shifted. When 8 bits is selected, the delay time is inserted after 8-bit
data is shifted. When IFS bits [9:0] are set to a value other than “0”, a delay is inserted between the characters. The length
of the delay inserted between characters is also changed by the IFSPSE bit of SPI Control Register 0 (SPCR0) as shown
below.
If the IFS value is “0”, seamless operation is performed. The SPI Module continues to shift data and supply a clock as long
as the software does not fall behind the transfer rate of the transmitter.
Rev. 3.1 November 1, 2005
SPICLK
(SPOL=0)
SPICLK
(SPOL=1)
SPIIN
SPIOUT
When SPCR0.IFSPSE=1: SPI Master Clock Cycle × IFS[9:0] × 32
When SPCR0.IFSPSE=0: SPI Master Clock Cycle × IFS[9:0]
idle
MSB
MSB
1
Sample point
2
B6
B6
Figure 20-3 Transfer Format when SPHA is “1”
3
B5
B5
4
B4
B4
20-6
5
B3
B3
6
B2
B2
7
B1
B1
Toshiba RISC Processor
LSB
LSB
8
idle
TX4939
20
20

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