TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 604

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SPI
20.4.4. SPI Interframe Delay Time Counter (SPFS)
Rev. 3.1 November 1, 2005
Default:
Default:
Bits
31 : 10
9 : 0
Name:
Name:
R/W:
R/W:
Bit:
Bit:
Mnemonic
⎯
IFS
31
15
30
14
RESERVED
29
13
Field Name
Reserved
Inter Frame
Space
Figure 20-7 SPI Interframe Delay Time Counter (SPFS)
Table 20-7 SPI Interframe Delay Time Counter (SPFS)
28
12
27
11
Description
⎯
Inter Frame Space (Default: 0x00)
This register sets the delay time to insert between two consecutive frames.
When this register is set to "0", transfer ends, the next transmission data is loaded
from the Transmitter FIFO to the Transmitter Buffer, and then the next transfer is
performed. (Since the time data is loaded into the buffer is not "0", the delay time
from the last clock until the first clock of the next transfer is not actually "0".)
When setting the IFSPSE bit of the SPCR0 Register to "0" and not using
prescaler, the Interframe delay time is the value calculated using the following
formula:
When setting the IFSPSE bit of the SPCR0 Register to "1" and using prescalar,
the Interframe delay time is the value calculated using the following formula:
Only write to this register when the SIDLE bit is "0".
26
10
25
9
(15 ns - 15.5 µs when SPI Master Clock Frequency is 66 MHz)
(480 ns - 496 µs when SPI Master Clock Frequency is 66 MHz)
20-12
RESERVED
24
8
23
7
22
6
0000000000
21
5
R/W
IFS
20
Toshiba RISC Processor
4
19
3
0xF80C
18
2
17
1
TX4939
16
0
20
20