TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 606

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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SPI
20.4.6. SPI Data Register (SPDR)
Rev. 3.1 November 1, 2005
Default:
Default:
Bit(s)
3
2
1
0
Bits
31 : 16
15 : 0
Name:
Name:
R/W:
R/W:
Bit:
Bit:
Mnemonic
IFSD
SIDLE
STRDY
SRRDY
Mnemonic
DR
31
15
30
14
29
13
Field Name
SPI Inter Frame
Space Delay
Indicator
SPI Idle Indicator
SPI Transmit
Ready
SPI Receive
Ready
Field Name
Reserved
SPI Data Register
28
12
27
11
Table 20-8 SPI Status Register (SPSR)
Figure 20-9 SPI Data Register (SPDR)
Table 20-9 SPI Data Register (SPDR)
Description
SPI Inter Frame Space Delay Indicator (Default: 0)
This bit becomes "1" when transfer of a frame ends and transfer of the next frame
is deferred by the Interframe Delay Time Counter.
0: No interframe cycle
1: Interframe cycle
SPI Idle Indicator (Default: 1)
This bit becomes "1" either when the Transmitter FIFO is empty or the SPSTP bit
is "1" and there is no transfer in progress.
0: Run
1: Idle
SPI Transmit Ready (Default: 1)
Indicates that there is space in the Transmitter FIFO.
0: Transmitter FIFO is full.
1: Transmitter FIFO has space.
SPI Receive Ready (Default: 0)
Indicates that there is reception data in the Receiver FIFO. This bit is cleared
when the SPDR Register is read and there is no longer any valid data in the
Receiver FIFO.
0: Receiver FIFO is empty.
1:There is data in the Receiver FIFO.
Description
SPI Data Register (Default: 0x00)
Register is empty, data is written to the Shift Register and transmission begins.
You can read the Receiver FIFO data when you read this register.
reading, the upper side (bits[15:8]) are "0".
26
10
The data written to this register is stored in the Transfer Buffer. When the Shift
When the transfer data size is 8 bits, use the lower 8 bits of this register. When
25
9
20-14
RESERVED
24
8
0x00
R/W
DR
23
7
22
6
21
5
20
Toshiba RISC Processor
4
19
3
0xF818
18
2
17
1
TX4939
16
0
20
20

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