TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 609
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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Toshiba RISC Processor
CIR
TX4939
21.3. Functional Description
21
21
21.3.1. Theory of Operation
All infrared (IR) remote controls use some kind of IR signal. The remotes transmit pulses of IR light to send the signal.
Demodulated signal connects to CIR signal of TX4939.
1) Pulse-Width-Coded Signals vary the length of pulses to code the information. If the pulse width is short then it
corresponds to a logical zero or a low. If the pulse width is long then it corresponds to a logical one or a high.
0
0
1
1
Figure 21-2 Pulse-Coded Signal
2) Space-Coded Signals vary the length of the spaces between pulses to code the information. In the Space-Coded
Signals, if the space width is short then it corresponds to a logical zero or a low. If the space width is long then it
corresponds to a logical one or a high.
0
1
1
Figure 21-3 Space-Coded Signal
The CIR samples the HIGH time and LOW time of the infrared signal. It then records these count (high and low) value
into registers. Upon L to H transition, it interrupt the CPU so that CPU can read these count value and determine if the
code is “1” or “0”.
The Interrupt can be program to either trigger at L to H transition or H to L transition of IR signal (default is L to H
transition).
The sample clock can be programmable. Refer to CIR register definition for more detail.
21.3.2. Signal Muxing
In TX4939, CIR signal is muxing with GPIO14/RXD3/SPIIN. In order to select CIR mode, firmware must select GPIO
mode (SPIMODE = 1 and SIO3MODE = 1) and then select GPIO14 as input mode (GPIOIMR[14]=0, GPIODR[14]=1).
Please refer to Chapter 7 Configuration for more detail.
Rev. 3.1 November 1, 2005
21-3
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