TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 61

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Features
1.1. Abstract
The TX4939 is a micro controller for the 64-bit TX System RISC TX49 family. The TX4939 uses the TX49/H4 core as its CPU.
The TX49/H4 core is a 64-bit RISC CPU core that Toshiba developed based on the R4000 architecture created by MIPS
Technologies, Inc. (MIPS). Refer to the TX49 Core Architecture Manual for more information on the TX49/H4 core such as
the Instruction set.
The TX4939 has as peripheral functions an External Bus Controller, a DDR SDRAM Controller, a PCI Controller, a DMA
Controller, an Interrupt Controller, an AC-link Controller, Serial and Parallel ports, a Timer/Counter, and peripheral circuits
such as Ethernet MAC, and RTC (Battery back-up capable).
1.2. Implemented Features
Rev. 3.1 November 1, 2005
TX49/H4 Core (On-chip IEEE754 Compliant Single/Double Precision FPU)
DDR SDRAM Controller (2 Channels: 32-bit/100-200MHz)
External Bus Controller (8-bit,16-bit with 4-channels)
NOR Flash Interface on External bus
NAND Flash Controller
32-bit PCI Controller (33 MHz/66 MHz) with 4 clock outputs, arbiter, and interrupts for 6 devices.
PCI Boot and Satellite mode
Direct Memory Access Controller (8 Channels [4 Channels are dedicated to ACLC])
SIO (4 Channels, ch2 and ch3 are multiplexed with SPI)
SPI (multiplexed with SIO ch2,ch3)
8-bit Video Port (Synchronous Parallel Interface)
Serial TS Video port (Max 3-ports)
Timer/Counter (6 Channels)
AC-link Controller / I2S(5.1ch) / I2S(2ch)
Ether MAC with RMII (2 Channels)
2-channel 100MB ATA IDE I/F
Security Engine - DES/3DES/AES/MD5/SHA1/Modular Exponentiation Operation/Ex-OR for FEC
Battery Backup RTC (48 bit linear counter, 250 bytes CMOS RAM)
Extensive Power Management Feature
Any Internal Controller can stop clock and keep RESET status.
On-chip SRAM (2 KB)
Interrupt controller (NMI, 4 external inputs for PCI and 3 external interrupt inputs for External Bus)
Low Power Consumption (Typ. TBD)
The TX4939 operates at 1.2 V (Internal), 2.5V(DDR) and 3.3 V (I/O Block), and supports the low power
consumption mode (Halt Mode).
Maximum Operating Frequency (for the CPU): 400 MHz
IEEE1149.1 (JTAG) Support: Debugging Support Unit
Built-in Clock Generator
20 MHz Single Xtal Operation
Generate All necessary Clock including Audio Sampling Clock Source
Audio Sampling 96, 48, 44.1, 32, 24, 22.05, 16, 8 KHz (x512)
Baud rate Clock source 14.7456 MHz
Package
PBGA 456 pins: 1.00 mm ball pitch
27 mm x 27 mm body size
36 pins are thermal ball for heat dissipation
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Chapter 1. Features
Toshiba RISC Processor
TX4939
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