TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 613

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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I2C
22.2.1. I2C Interrupt Control/Status Register (I2C_ICTSR)
Rev. 3.1 November 1, 2005
Bit
31:16
15:8
7
6
5
4
3:2
1
0
Reset Value
Reset Value
R/W/RO
R/W/RO
Bit
Bit
RO
RO
31
15
0
0
Field Name
Reserved
Reserved
I2C_ASTS
I2C_DSTS
I2C_AINTFL
I2C_DINTFL
Reserved
I2C_AEN
I2C_DEN
RO
RO
30
14
0
0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Description
I2C Ack Flag
I2C Done flag
I2C Ack interrupt flag
Write “1” to clear, write “0” has no affect.
I2C Done interrupt flag
Write “1” to clear, write “0” has no affect
I2C Detect ACK interrupt enable
When this bit set, controller will generate interrupt when it detects
missing ACK during transfer. This bit is disabled when I2C controller is
in Byte mode.
I2C control done interrupt enable
When this bit set, controller will generate interrupt when it is done with
the transfer.
RO
RO
27
11
0
0
0: Acknowledge received.
1: No Acknowledge received
0: Idle/Done
1: BUSY
0: Normal
1: Interrupt occur
0: Normal
1: Interrupt occur
0: Disabled
1: Enabled
0: Disabled
1: Enabled
RO
RO
26
10
0
0
22-3
RO
RO
25
0
9
0
RO
RO
24
0
8
0
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
5
0
0
RO
RO
20
0
4
0
Toshiba RISC Processor
RO
RO
19
3
0
0
RO
RO R/W R/W
18
0
2
0
0xF900
RO
17
1
0
0
RO
16
0
0
0
TX4939
22
22

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