TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 622

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2C
22.7. Bit Command Controller
The Bit Command Controller handles the actual transmission of data and the generation of the specific levels for START,
Repeated START, and STOP signals by controlling the SCL and SDA lines. The Byte Command Controller tells the Bit
Command Controller which operation has to be performed. For a single byte read, the Bit Command Controller receives
8 separate read commands. Each bit-operation is divided into 4 pieces, except for a STOP operation which is divided into
3 pieces.
22.8. Data IO Shift Register
The DataIO Shift Register contains the data associated with the current transfer. During a read action, data is shifted in
from the SDA line. After a byte has been read the contents are copied into the Receive Register. During a write action,
the Transmit Register’s contents are copied into the DataIO Shift Register and are then transmitted onto the SDA line.
Rev. 3.1 November 1, 2005
Start
Rep Start
Stop
Write
Read
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
Figure 22-6 Bit Command Control
A
22-12
B
C
D
Toshiba RISC Processor
TX4939
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