TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 623

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
I2C
22.9. Programming Examples
22.9.1. Example 1 (Byte Mode)
Write 1 byte of data to a slave.
Slave address = 0x51 (b”1010001”)
Data to write = 0xAC
I2C Sequence:
Commands:
Rev. 3.1 November 1, 2005
SCL
SDA
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
generate start command
write slave address + write bit
receive acknowledge from slave
write data
receive acknowledge from slave
generate stop command
write 0xA2 (address + write bit) to Transmit Register, set STA bit, set WR bit.
read I2C_ASTS (ACK) bit from Control/Status Register, should be ‘0’.
write 0xAC to Transmit register, set STO bit, set WR bit.
read I2C_DSTS (ACK) bit from Status Register, should be ‘0’.
S
-- wait for interrupt or I2C_DSTS flag to negate –
-- wait for interrupt or I2C_DSTS flag to negate –
First Command
Figure 22-7 Byte Mode
Wr ack
22-13
Second Command
Toshiba RISC Processor
ack
P
TX4939
22
22

Related parts for TX4939XBG-400