TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 625

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.1. Overview
I2SC is an interface between G-bus and I
one I
The basic features of the I2SC are outlined below:
Rev. 3.1 November 1, 2005
2
S output.
Interface to 32-b IMB bus.
Two modes of operation (2 channels i/o mode, 3 Channel output mode)
Support 16, 18, 20 or 24 bits data.
Support Left or Right-justify with MSB first or LSB first.
Support 32, 48 or 64 bit-wide time-slot.
(Input/Output)
Control
I2S IF
FIFO
I2S
Figure 23-1 the block diagram of the I2SC Interface module.
(Input/Output)
Control
I2S IF
FIFO
2
I2S
S protocol. This controller supports two programmable I
IMBus
Gbus Interface & DMA Interface
23-1
(Output)
Control
I2S IF
FIFO
Chapter 23. I2S Controller
I2S
DMAC
Toshiba RISC Processor
Registers
I2S
2
S output/input, and
TX4939
23
23