TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 627

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.2. I2S Function
23.2.1. I
I
a clock line. Since the transmitter and receiver have the same clock signal for data transmission, the transmitter as the
master, has to generate the bit clock (SCK), and word-select (WS). Figure 23-3 illustrates simple system configurations
and the basic interface timing.
Note that the time-slot (1/fs) could be 64, 48, or 32 bit-wide. Input data could be 16, 18, 20 or 24 bits and could be left- or
right-justify with MSB first or LSB first. There are three formats shown in Figure 23-3. Figure 1.3(a) illustrates Standard
Data Format (Sony Format) with Left-Channel “H” and Right-channel “L”, (b) Left Justified Format with Left-channel “L” and
Right-channel “H”. For I
Rev. 3.1 November 1, 2005
2
S bus is a 3-pin serial link consisting of a line for two time multiplexed data channels (left and right), a word select line and
2
S Interface
Transmitter
2
S data format, there is one clock delay to latch the data bit.
Word select
Clock
WS
SCK
Data
SD
Transmitter-Master
Right Channel
WORD n-1
SCK
WS
SD
MSB
Figure 23-3 I
Receiver
23-3
Left Channel
WORD n
2
S Interface
Transmitter
Receiver-Master
LSB
SCK
WS
SD
MSB
Right Channel
WORD n+1
Toshiba RISC Processor
Receiver
TX4939
23
23