TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 631

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.2.3. MCLK and SCK Clock
SCK derived from Master Clock (MCLK). Internal to TX4939, there are an Audio Clock Generator. This Clock Generator
will generate two Master Clock (MCLK0 and MCLK1). MCLK0 uses in 3 channel output modes. Both MCLK0 and MCLK1
use in 2 channels i/o mode.
The source of MCLK0 and MCLK1 can be from internal Audio Clock Generator or external clock source. I2S Channel
Control Register has two bits to control these options for MCLK0 and MCLK1. Bit[23] selects clock source for MCLK1,
bit[[7] selects clock source for MCLK0.
* Internal Audio Clock Generator generates the following frequency
* There are two options for SCK clock source.
First option is Master mode, SCK is internally derived from the Master Clock (MCLK). The divider is used to generate SCK
clock. Divider value is in I2SDIV register.
Second option is Slave mode. SCK is from external source. MCLK is not use in this mode.
* The following shows the divider value for different sample rate and different time slot.
Figure 23-7 shows the relation between MCLK and SCK with Divider value = 2,3,4
Rev. 3.1 November 1, 2005
24.5760Mhz, 22.5792Mhz, 16.3840Mhz, 14.7456Mhz, 12.2880Mhz, 8.1920Mhz, 4.0960Mhz
768x
512x
384x
256x
192x
128x
96x
64x
Sample Rate
0
1
0
1
Bit[23]
Bit[7]
24
N/A
12
8
6
4
3
2
32-bit
Slave - External clock
Master - Internal clock
Slave - External clock
Master - Internal clock
MCLK1
MCLK0
23-7
N/A
N/A
8
N/A
4
N/A
2
N/A
Time Slot
48-bit
Input
Output
Input
Output
MCLK1 IO pad
MCLK0 IO pad
12
8
6
4
3
2
N/A
1
Toshiba RISC Processor
64-bit
TX4939
23
23