TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 632

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.2.4. MCLK and WS Detection
In I2S controller, there is logic that checks MCLK and WS clock frequency.
For MCLK detection, fast clock (150 MHz) uses to sample the MCLK clock. At every rising edge of MCLK, the counter
begins to count (from “0”) base on 150 MHz clock. And also at every rising edge of MCLK, this count value get compare
with the MCLK check value (register bits). If the count value is greater then MCLK check value, which means MCLK is out
of range, Interrupt will get set. Otherwise it continues sampling MCLK. Once out of range detect, counter logic will stop
counting.
For the WS detection, the logic simply samplings the WS with SCK clock. At every rising and falling edge of WS, counter
starts counting from “0” base on SCK clock. It also compares the counter value at every rising edge of WS. If counter
value match the setting in the control register (time slot – 32, 48, 64) means WS frequency is correct. If counter value does
not match, WS interrupt sets to high and counter logic detection stops counting.
Rev. 3.1 November 1, 2005
(DIV = 2)
MCLK
(DIV = 3)
(DIV = 4)
SCK
SCK
SCK
Figure 23-7 MCLK and SCK with Divider Value
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Toshiba RISC Processor
TX4939
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