TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 636

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

I2S
23.4.3. I2S Channel Control Register (I2SCCR)
Rev. 3.1 November 1, 2005
Bit
D31
D30:28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18:17
Reset Value
Reset Value
R/W/RO
R/W/RO
Bit
Bit
R/W RO
RO
31
15
0
0
Field Name
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RO
30
14
0
0
RO
RO
29
13
0
0
RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
28
12
0
0
Description
I2S mode option
Reserved.
WS Check Enable (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
MCLK Check Enable (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
Clock Data Option (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
Notes:
Falling edge selected: WS is toggle at the falling edge of SCK
Rising edge selected:
Output mode:
Input mode:
Data Channel Swap Option (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
MCLK Mode Option (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
Receiver-Master Mode Option (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
Clock Delay Option (Channel 1 i/o mode)
For Left-Justify mode only
When 3 Channel Mode is enable, this bit is not used
Invert WS Option (Channel 1 i/o mode)
Invert WS right at the IO pad.
When 3 Channel Mode is enable, this bit is not used
Left/Right Justify Select Option (Channel 1 i/o mode)
When 3 Channel Mode is enable, this bit is not used
Data Select Option (Channel 1 i/o mode)
When 3 Channel Mode is enable, these bits are not used
27
11
0
0
Falling edge selected: clock SD
Rising edge selected: clock SD at rising edge
Falling edge selected: sample SD at rising edge
Rising edge selected: sample SD
26
10
0
0
23-12
0:
1:
0: Disable (default)
1: Enable
0: Disable
1: Enable
0: Falling edge (default)
1: Rising edge
0: Left-Justify (default)
1: Right-Justify
00: 16 bits data (default)
01: 18 bits data
10: 20 bits data
11: 24 bits data
0: Normal (default)
1: Swap (MSB <--> LSB)
0: Slave mode. Receive MCLK1
1: Master mode. Drive MCLK1 (Default)
0: Slave mode. Receive SCK, WS
1: Master mode. Drive SCK, WS (Default)
0: Latch data on the first clock (default)
1: Latch data on the second clock
0: As normal (default)
1: Invert WS
25
0
9
0
2 channel i/o mode (default)
3 channel output mode
24
0
8
0
WS is toggle at the rising edge of SCK
23
1
7
1
22
1
6
1
21
0
5
0
at falling edge
at falling edge
20
0
4
0
Toshiba RISC Processor
19
3
0
0
18
0
2
0
0xFA04
17
1
0
0
16
1
0
1
TX4939
23
23