TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 644

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.2. Configuration
Figure 24-1 illustrates the ACLC configuration.
24.3. Functional Description
ACLC provides four mechanisms to operate AC’97-compliant CODEC(s):
This section first describes the CODEC connection, chip configuration, and overall usage-flow.
sequence and the other mechanisms will be described.
Rev. 3.1 November 1, 2005
AC-link status control (start-up and low-power mode)
CODEC register access
Sample-data transmission and reception
GPIO operation
DMAC
Data I/O Master
Slot-data
Transfer
Bitstream Receive & Transmit
aclcimtop
aclcimbif
Asynchronous Handshake
AC-link
Bus I/F
IM-bus
Figure 24-1 ACLC Module Configuration
Slot Valid/Req &
Register Access
aclc
Slave Register
24-2
Using low-power mode comes last.
Wake-UP
Control
Toshiba RISC Processor
(BITCLK / ACRESET*)
(imclk / imreset* )
System-side
Then AC-link start-up
Link-side
TX4939
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