TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 655

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.3.6.3. Sample-data FIFO
For a transmission stream, as long as ACLC Control Enable Register (ACCTLEN) allows that transmission and the FIFO
has any room to fill data in, the FIFO issues a request via the REQ latch.
receives a data-request from the link-side, it provides data with valid-flag set if it has any valid data.
data, it responds with valid-flag unset and an underrun error bit is set.
At the transmit-data DMA start-up, until the FIFO becomes full, it responds to the link-side with valid-flag unset, in order
to maximize the buffering effect.
The link-side drives the slot-valid bit and slot-data on AC-link.
For a reception stream, as long as the FIFO has any valid data, the FIFO issues a request via the REQ latch.
other side, when ACCTLEN allows that reception and the link-side issues a data strobe, the FIFO stores the valid data.
If the FIFO is full when it receives a data strobe, the data is discarded and an overrun error bit is set.
24.3.6.4. Error Detection and Recovery
In most usages, since the CODEC continuously requests sample-data transmission and reception, after DMA is finished,
underrun and overrun will occur.
occurred during DMA operation.
The software sets ACLC Control Enable Register (ACCTLEN)’s Error Halt Enable (xxxxEHLT) bit before it starts a DMA
channel.
Overrun Error (xxxxERR) bit is set.
(DMCCRn)’s Transfer Active (XFACT) bit and ACLC DMA Request Status Register (ACDMASTS)’s Request (xxxxDMA)
bit and determines the DMA completion status as follows.
To recover from error, disable and enable the stream via ACCTLEN, and restart the DMA.
Rev. 3.1 November 1, 2005
After it starts the DMA channel, it waits until ACLC Interrupt Status Register (ACINTSTS)’s Underrun or
DMCCRn.XFACT
Inactive
Inactive
Active
Table 24-9 DMA Completion Status Determination
Therefore, the DMA size must be the FIFO depth or more.
The procedure described below allows the software to determine whether an error has
When the event is detected, the software checks DMA Channel Control Register
PCM L&R out
Surround L&R out
Center out
LFE out
Modem Line 1 out
Table 24-8 Transmission FIFO Depth
Data-stream
ACDMASTS.xxxxDMA
Pending
Not Pending
*
24-13
FIFO Depth (Word)
When underrun occurs, these bits are driven to all ‘0’.
3
3
2
2
1
On the other side, when a transmission FIFO
Completion Status
No Error during DMA
Underrun or Overrun
Underrun or Overrun
Toshiba RISC Processor
If it has no valid
TX4939
On the
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