TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 657

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.3.8. Interrupt
ACLC generate two kinds of interrupt to the interrupt controller as below.
24.3.9. AC-link Low-power Mode
The AC’97 specification makes provision for saving power during system suspension by powering-down both the
controller and CODEC except the minimum circuit to detect modem RING/Caller-ID event and wake up the system.
AC’97 CODEC is required to go into the low-power mode when they receive a special register-write access.
mode, the AC-link controller must drive all output signals to low level to allow the CODEC digital I/O power cut.
ACLC provides ‘AC-link low-power mode’ setting.
(ACCTLEN)’s Enable AC-link Low-power Mode (LOWPWR) bit, all the output signals except the ACRESET* signal to the
AC-link are forced to low level.
The AC-link will be reactivated out of the low-power mode when the SYNC signal is driven high for 1 µs or longer by the
AC-link controller while the BITCLK signal is inactive.
period.
ACLC also provides the ‘wake-up’ function.
(WAKEUP) bit, high-level input at any SDIN[x] signal will force ACLCPME interrupt assertion.
When ACLCPME interrupt is recognized, the software must disable the low-power mode and assert warm reset to the
AC-link via ACCTLEN Register’s Enable Warm Reset (WRESET) bit. After the warm reset is deasserted, the CODEC will
start providing the BITCLK signal, and then ACLC will generate the SYNC signal for usual AC-link frames.
Refer to section B.5.1 of AC’97 specification revision 2.1 for the power-down and wake-up sequence in AC-link
power-down mode.
Rev. 3.1 November 1, 2005
ACLC Interrupt
Logical OR of all the valid bits of ACLC Interrupt Masked Status Register (ACINTMSTS) is connected. Refer to
the section 24.4.5.
ACLCPME Interrupt
This interrupt shows the wake-up from CODEC in AC-link low-power mode.
Refer to the description for ACLC Control Enable Register (ACCTLEN)’s Wake-up Enable (WAKEUP) bit in
section 24.4.6.
While this function is enabled by ACCTLEN Register’s Enable Wake-up
When this mode is enabled by ACLC Control Enable Register
24-15
The software is responsible for controlling the length of this
Toshiba RISC Processor
In this
TX4939
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