TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 662

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ACLINK
Rev. 3.1 November 1, 2005
Bit
3
2
1
0
Mnemonic
WRESET
WAKEUP
LOWPWR
ENLINK
Field Name
Assert Warm
Reset
Enable Wake-up
Enable AC-link
low-power mode
Enable AC-link
Description
WRESET: Assert Warm Reset.
WAKEUP: Enable Wake-up.
LOWPWR: Enable AC-link Low-power Mode.
ENLINK: Enable AC-link.
R
W1S
Note 1: Do not assert warm reset during normal operation.
Note 2: The software must guarantee the warm reset assertion time
R
W1S
Note:
R
W1S
Note:
R
W1S
Note:
Table 24-11 ACCTLEN Register
0:
1:
0:
1:
meets the AC’97 specification (1.0 µs or more).
0:
1:
0:
1:
Do not enable wake-up during normal operation.
0:
1:
0:
1:
Do not enable AC-link low-power mode during normal
operation.
0:
1:
0:
1:
The software must guarantee the ACRESET* signal
assertion time meets the AC’97 specification (1.0 µs or
more).
Indicates that warm reset is not asserted.
Indicates that warm reset is asserted.
No effect
Asserts warm reset.
Indicates that wake-up from low-power mode is
disabled.
Indicates that wake-up from low-power mode is
enabled.
asserts ACLCPME interrupt request to the interrupt
controller.
No effect
Enables wake-up from low-power mode.
SYNC and SDOUT signals are not forced to low.
SYNC and SDOUT signals are forced to low.
No effect
Forces SYNC and SDOUT signals low.
Indicates that the ACRESET* signal to AC-link is
asserted.
Indicates that the ACRESET* signal to AC-link is not
asserted.
No effect
Deasserts the ACRESET* signal to AC-link
24-20
While any SDIN signal is driven high, ACLC
Toshiba RISC Processor
R/W
R/W1S
R/W1S
R/W1S
R/W1S
TX4939
24
24

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