TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 665

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
Rev. 3.1 November 1, 2005
Bit
0
Mnemonic Field Name
—
Clear xxxxDMA bits in ACCTLEN to “0” by using this register to disable transmit/receive-data
DMA and to stop transmission/reception by the AC-link. Note that if these bits are cleared while
output-slot data is flowing in the FIFO, ACLC may output a wrong data as the last sample. This
behavior will not occur if the software waits for data-flow completion by detecting underrun
before it disables the corresponding slot.
Description
ENLINK: Disable AC-link.
W1C
Note : The software must guarantee the ACRESET* signal assertion
Table 24-12 ACCTLDIS Register
0:
1:
time meets the AC’97 specification (1.0 µs or more).
No effect
Asserts the ACRESET* signal to AC-link.
24-23
IMPORTANT NOTE
Toshiba RISC Processor
Read/Write
W1C
TX4939
24
24