TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 666

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ACLINK
24.4.3. ACLC CODEC Register Access Register
CODEC registers can be accessed through this register.
Rev. 3.1 November 1, 2005
Bit
31
30:26
25:24
23
22:16
15:0
Default:
Default:
Name:
Name:
R/W:
R/W:
Bit:
Bit:
Mnemonic Field Name
CODECRD
CODECID
REGADR
REGDAT
CODE
CRD
31
15
W
30
14
AC’97 register read
access
Reserved
AC’97 CODEC ID
Reserved
AC’97 register
address
AC’97 register data REGDAT: AC’97 register data
This register must not be read from or written to until access completion is reported through the
ACINTSTS register.
29
13
Reserved
28
12
27
11
Description
CODECRD: AC’97 register read access
CODECID: AC’97 CODEC ID
Specifies the CODEC ID of the read/write access destination.
REGADR: AC’97 register address
Read
Write
Read
Write
Write
Write
Note : The software must guarantee the ACRESET* signal assertion
26
10
Figure 24-11 ACREGACC
Table 24-13 ACREGACC
0:
1:
time meets the AC’97 specification (1.0 µs or more).
Read address. Valid address can be read after read access is
complete.
Specifies the read/write access destination address.
Valid data can be read after read access is complete.
Write Data
The values “0” through “3” can be specified as the CODEC ID,
but the number of CODECs actually supported depends on
the configuration.
25
CODECID
Indicates a write access.
Indicates a read access.
9
24-24
R/W
IMPORTANT NOTE
24
REGDAT
8
0x00
R/W
Reserved
23
7
22
6
21
5
20
Toshiba RISC Processor
4
REGADR
R/W
19
3
0xF708
18
2
Read/Write
W
W
R/W
R/W
17
1
TX4939
16
0
24
24

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