TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 668

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
Rev. 3.1 November 1, 2005
Bit
9
8
7:6
5
4
3:2
1
0
Mnemonic
SURRERR
AUDOERR
⎯
GPIOINT
REGACCRDY
⎯
CODEC1RDY
CODEC0RDY
Field Name
Audio Surround
L&R
Transmit-data
DMA Underrun
Audio PCM L&R
Transmit-data
DMA Underrun
Reserved
GPIO Interrupt
ACREGACC
Ready
Reserved
CODEC1 Ready
CODEC0 Ready
Description
SURRERR: Audio Surround L&R Transmit-data DMA Underrun
AUDOERR: Audio PCM L&R Transmit-data DMA Underrun
GPIOINT: GPIO Interrupt
REGACCRDY: ACREGACC Ready
CODEC1RDY: CODEC1 Ready
CODEC0RDY: CODEC0 Ready
Read
W1C
Read
W1C
Read
W1C
Read
W1C
Read
Read
Table 24-14 ACINTSTS Register
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
No activity
Indicates that the audio surround L&R transmit-data DMA
underrun.
No activity
This bit is cleared when “1” is written to it.
No activity
Indicates that the audio PCM L&R transmit-data DMA
underrun.
No activity
This bit is cleared when “1” is written to it.
No activity
Indicates that the incoming slot 12 bit[0] is ‘1’ (the modem
CODEC GPIO interrupt).
No activity
This bit is cleared when “1” is written to it.
No activity
Indicates that the ACREGACC register is ready to get the
value (in case the previous operation was a read access)
and to initiate another R/W access to an AC’97 register.
The result of reading or writing to the ACREGACC
register before the completion notification is undefined.
This bit is cleared if “1” is written to it.
No activity
This bit automatically becomes ‘0’ when the ACREGACC
register is written.
No activity
Indicates that the CODEC Ready bit of SDIN1 Slot0 is
set.
No activity
Indicates that the CODEC Ready bit of SDIN0 Slot0 is
set.
24-26
Toshiba RISC Processor
R/W
R/W1C
R/W1C
⎯
R/W1C
R/W1C
⎯
R
R
TX4939
24
24