TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 669

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ACLINK
24.4.5. ACLC Interrupt Masked Status Register
Every bit in this register is configured as follows:
Bit placement is the same as for the ACINTSTS register.
interrupt request to the interrupt controller.
24.4.6. ACLC Interrupt Enable Register
Interrupt request enable (R/W1S).
When a value is written to this register, the bit in the position where “1” was written is set to “1.”
24.4.7. ACLC Interrupt Disable Register
Interrupt request enable clear (W1C).
written to this register, the ACINTEN register bit in the position where a “1” was written is cleared to “0.”
Rev. 3.1 November 1, 2005
ACINTMSTS = ACINTSTS & ACINTEN
Bit placement is the same as for the ACINTSTS register.
Bit placement is the same as for the ACINTSTS register.
24-27
The logical OR of all bits in this register is used as ACLC
Toshiba RISC Processor
Its initial value is all ‘0’.
When a value is
0xF714
0xF718
0xF71C
TX4939
24
24