TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 67

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

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2.3. Power Management Feature
TX4939 has extensive power management features, which will enable to develop ultimate low power system.
Those features are:
2.3.1. Strategy for Power Management
In general, there are two major strategies to reduce total chip power consumption, such as (1) switching the clock frequency
between normal and some of reduced one and (2) switching the CPU operation mode between normal and power save
mode. These changing will be controlled by CPU by observing the system situation.
In case of TX4939 SoC, because of the complexity of clock generator, which produces all necessary clocks out of one 20
MHz clock source by cascading two PLL, it is not practical to switch the clock frequency to another on the fly.
So that, CPU operation mode switching will be used for CPU power management in conjunction with peripheral operation
mode switching described below.
2.3.2. Power Management for Internal Controller
The most of internal controller has power management facilities. Such as Clock Disable and Resetting. Table 2-1 lists the
whole control bits.
2.3.3. Battery Back-Up Real Time Clock
TX4939 has a battery back-up Real Time Clock with alarm function. This alarm function generates interrupt signal both
CPU and external terminal. The external interrupt signal can wake the CPU up by the help of external power control circuit.
This RTC is designed as low power circuitry which consumes 5 uA at maximum. This assures 10 years battery life with
conventional Lithium battery with 200 mAH capacity. The ultimate low power system can be realized with this RTC.
Rev. 3.1 November 1, 2005
CLOCK
ETH2CKD
ETH1CKD
BROMCKD
NDCCKD
I2CCKD
ETH0CKD
SPICKD
SRAMCKD
PCIC1CKD
DMA1CKD
ACLCKD
ATA0CKD
DMA0CKD
PCICKD
I2SCKD
TM0CKD
TM1CKD
TM2CKD
SIOCKD
CYPCKD
Power Management in TX49/H4 CPU Core.
Internal Controller Clock and Status Control
Battery Back-Up Real Time Clock
RESET
ETH2RST
ETH1RST
BROMRST
NDCRST
I2CRST
ETHC0RST
SPIRST
SRAMRST
PCIC1RST
DMA1RST
ACLRST
ATA0RST
DMA0RST
PCICRST
I2SRST
TM0RST
TM1RST
TM2RST
SIORST
CYPRST
Table 2-1 Periphheral Clock and Reset Control
DESCRIPTION
Clock Stop or Hold Reset the Ethernet MAC 2
Clock Stop or Hold Reset the Ethernet MAC 1 controller.
Clock Stop or Hold Reset the NAND Flash controller.
Clock Stop or Hold Reset the I2C controller.
Clock Stop or Hold Reset the SPI controller.
Clock Stop or Hold Reset the SRAM controller.
Clock Stop or Hold Reset the PCI controller 1.
Clock Stop or Hold Reset the DMA controller 1.
Clock Stop or Hold Reset the AC-link controller.
Clock Stop or Hold Reset the ATA0 controller.
Clock Stop or Hold Reset the DMA controller 0.
Clock Stop or Hold Reset the PCI controller.
Clock Stop or Hold Reset the I2S controller.
Clock Stop or Hold Reset the TMR0 controller.
Clock Stop or Hold Reset the TMR1 controller.
Clock Stop or Hold Reset the TMR2 controller.
Clock Stop or Hold Reset the SIO controller.
Clock Stop or Hold Reset the Cipher controller.
Clock Stop or Hold Reset the BROM/SRAM controller.
Clock Stop or Hold Reset the Ethernet MAC 0 controller.
2-3
Toshiba RISC Processor
COMMENT
TX4939
2
2