TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 68

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

BLOCK
2.4. TX4939 Peripheral Function Features
Rev. 3.1 November 1, 2005
Direct Memory Access Controller (DMAC)
Has an on-chip 8-channel DMA Controller. Three of channels execute DMA transfer to memory and I/O devices,
and the rest of 5-channels are for internal resources (one for NAND Flash and 4 channels are dedicated for
ACLC/I2S).
□ Each of the 3 memories and I/O device channels can respond to internal/external DMA requests.
□ Has an on-chip 4-channel DMA Controller dedicated to ACLC/I2S and an on-chip 1-channel DMA Controller
□ Supports DMA transfer between the on-chip Serial I/O Controller and AC-Link Controller as internal DMA
□ Supports transfer between external I/O devices and memory with 16-bit or 8-bit data bus.
□ Supports modes for copying between memories that have no address boundary restrictions.
□ Supports modes for writing double word data in the specified memory region and filling memory.
□ Supports Chain DMA transfer.
DDR SDRAM Controller (DDRC)
The DDR SDRAM Controller generates the clock and control signals that are required by the DDR SDRAM
interface. The DDR SDRAM Controller has 2 on-chip channels and can support memory sizes of up to 2GB
(1GB/Channel) by supporting various memory configurations.
NOTE: Motherboard for the memory configuration more than 4-chips or 1-GB should be carefully designed.
□ Memory Clock Frequency: from 100 MHz to 166 MHz, and 200MHz
□ 2 Independent Memory Channels
□ Supports 2/ 4-bank 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1 Gb DDR SDRAM.
□ 256Mbit (x16)
□ 512Mbit (x16)
□ 256Mbit (x16)
□ 1Gbit (x16)
□ 256Mbit (x8)
□ 1Gbit (x8)
□ Data bus width is 32 bits.
□ Advanced Memory Mapping Technology
for internal resource
requests.
Burst transfers of up to 8 double words are possible for a single read or write operation.
One kind of DDR SDRAM timing set for all channel
Supports critical word first access of the TX49/H4 core.
Low power consumption mode: Can select Self-refresh or Pre-charge Power Down.
4 (four) independent DDR memory mapping windows enable mapping the DDR memory space to anywhere
TX49 physical memory space with 16 MB resolution.
2pcs
2pcs
4pcs
4pcs
4pcs
8pcs
2-4
(=64MB)
(=128MB)
(=128MB)
(=512MB)
(=128MB)
(=1GB)
(Max capacity with x16 chip)
(Max capacity with x8 chip)
Toshiba RISC Processor
TX4939
2
2