TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 687

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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SRAM
25.1. Characteristics
The TX4939 has 1-channel of on-chip, fast 2-KB SRAM. You can map it to any address space by setting the Base
Address Register. You can access SRAM from each G-Bus Master: the TX49/H4 core, DMAC0, DMAC1, PCI0, and PCI1.
25.2. Block diagram
1 : On-chip SRAM does not support special Burst access (address decrementing/fixed) of DMAC0, DMAC1.
Rev. 3.1 November 1, 2005
2 KB
Specifiable base address
Accessible in Byte, half-word, word, or double-word units
Supports Burst access1
×
1 channel
G-Bus
Figure 25-1 On-chip SRAM Block Diagram
G-Bus I/F
25-1
On-chip SRAM
Chapter 25. On-Chip SRAM
Memory
2 KB × 1
Toshiba RISC Processor
TX4939
25
25
25
25

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