TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 693

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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CRYPT
26.2.2. CIPHER DMA Controller
The CIPHER DMA Controller has the following features:
The CIPHER’s DMA engine has one channel to transfer data between memory and the CIPHER engine.
There are four tasks for the DMA:
26.2.2.1. DMAC Theory of Operations
The CIPHER’s DMA engine deploys the following algorithm:
Rev. 3.1 November 1, 2005
1. To get a descriptor
2. To update the status in a descriptor when transfer complete
3. To transfer transmitted data from Transmit FIFO to memory (TxFIFO(8bytes x 16) – output buffer)
4. To transfer received data from memory to Receive FIFO (RxFIFO (8bytes x 16) – input buffer).
1. Firmware programs the six sets of Keys and Initial data.
2. The ENCR bit of the CSR register is set to start the DMA controller (DMAC).
3. DMAC fetches the first descriptor located at a memory location pointed to by the CDESPtr
4. DMAC is ping-pong between input buffer and output buffer to make sure deadlock does not
5. DMAC completes transmit data transfer (when both input and output byte counts reach “0”).
6. DMAC proceeds to the next descriptor if the next descriptor pointer is not ‘h0000_0000.
7. When G-bus error occurs or Time-out occurs, DMA controller will stop all transfer.
Supports register access
Supports master mode for G-bus protocol (single and burst transfer)
Supports chain and link list DMA protocol
Supports un-alignment byte data transfer for both input and output DMA transfer
register.
occur.
Otherwise, DMAC will stop and clear the ENCR bit in the CSR register.
26-3
Toshiba RISC Processor
TX4939
26
26

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