TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 696

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

CRYPT
26.2.2.4. Initial Descriptor Pointer Register (IDESPtr)
26.2.2.5. Current Cipher Descriptor Pointer Register (CDESPtr)
26.2.2.6. Time Out Register (cip_tout)
26.2.2.7. Bus Error Address Register (BusErr)
26.2.2.8. XOR Source Lower Register 0(XORSLR)
26.2.2.9. XOR Source Upper Register 0(XORSUR)
Rev. 3.1 November 1, 2005
Notes: This register is for testing purpose only
Notes: need to issues software reset (DMAC reset - RSTD),to clear BusErr register.
Bit(s)
31:0
Bit(s)
31:0
Bit(s)
31:8
7:0
Bit(s)
31:20
31:2
1
0
Bit(s)
31:0
Bit(s)
31:0
Field
Field
--
Field
–
Field
–
--
Field
Field
--
--
--
--
--
--
Table 26-4 Current Cipher Descriptor Pointer Register (CDESPtr)
R/W
R/W
R/W
RO
R/W
RO
R/W
R/W
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Table 26-3 Initial Descriptor Pointer Register (IDESPtr)
Table 26-7 XOR Source Lower Register 0(XORSLR)
Table 26-8 XOR Source Upper Register 0(XORSUR)
Table 26-6 Bus Error Address Register (BusErr)
Default
32’h0
Default
32’h00
Table 26-5 Time Out Register (cip_tout)
Default
0
8’h00
Default
0
0
0
0
Default
0
Default
0
Description
Initial Descriptor Pointer
This pointer will point to the first descriptor address.
Description
When Crypt engine is running.
address of the descriptor that the engine is current processing.
Description
Reserved
Programmable Time Out
If timer reach 0 before see “ACK” from Cipher engine. Then it will
generate Timeout error.
and start count down again.
8’h00 = disable timer
8’h01 – 8’hff = timer count
These counters clock by GBUSCLK
Description
Reserved
G-bus error address[31:2]
Command status during bus error.
0: Write operation
1: Read operation
When set, indicates the address is valid, i.e. Bus Error has been
captured.
Description
XOR Source Lower Register
Lower 32 bit of the XOR source data which used to XOR with the
bit stream
Description
XOR Source Upper Register
Upper32 bit of the XOR source data which used to XOR with the
bit stream
26-6
Upon receive “ACK” then reload timer
This register points to the
Toshiba RISC Processor
TX4939
26
26