TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 70

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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BLOCK
Rev. 3.1 November 1, 2005
8-bit Video Port, 3-Serial Video ports
MPEG-2 stream IO port based on Bt.656 protocol
CrYCb Video Capture and Streaming
SPI
□ Full duplex, synchronous serial data transfer (I/O data, clock signals)
□ Can specify 8-bit or 16-bit data length
□ Programmable SPI baud rate
□ Supports Master mode only
Commercial IR(CiR) (This feature shares pin with SIO-3)
The commercial IR for remote controller.
Timer/Counter Control (TMR)
Has on-chip 3-channel timer/counter.
□ 32-bit up counter
□ Supports 3 modes (Interval Timer Mode, Pulse Generator Mode, Watchdog Timer Mode).
□ Timer Output Pins: 2 pins
□ Count Clock Input Pins: 1 pin
□ Watchdog External Reset Signals: 1 signal
AC-link Controller (ACLC) (same function with TX4937/38, but pins are shared with I2S)
The AC-link Controller can connect to and manipulate audio and/or modem CODECs described in “Audio
CODEC ’97 Revision 2.1” (AC’97).
□ Supports up to 2 CODECs.
□ Supports 16-bit PCM left-right channel recording and playback.
□ Supports 16-bit surround, center, and LFE channel playback.
□ Supports variable rate audio recording and playback.
□ Supports modem CODEC Line 1 and GPIO slot.
□ Supports AC-link low power mode, wakeup, and warm reset.
□ Supports sample data input/output by DMA transfer.
I2S Audio CODEC Interface (I2S) (This feature shares pin with AC-Link)
The I2S controller supports two programmable I2S output/input, and one I2S output.
The basic features of the I2S controller are outlined below:
□ Two modes of operation (2 channels i/o mode, 3 Channel output mode)
□ Support 16, 18, 20 or 24 bits data.
□ Support Left or Right-justify with MSB first.
□ Support 32, 48 or 64 bit-wide time-slot.
×
3 channels
2-6
Toshiba RISC Processor
TX4939
2
2

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