TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 700

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
CRYPT
Rev. 3.1 November 1, 2005
Field
31:21
20:10
9
8
7:5
4
3
2:1
0
Field
31:7
6:4
[3]
2:0
Notes:
If Encryption and Hash together then program both IndexA and IndexB
Name
ObyteCount[10:0]
IbyteCount[10:0]
Start_packet
End_packet
---
Xor_sel
Last_data
Error
---
Name
---
IndexB[2:0]
--
IndexA[2:0]
If only Encryption then program only IndexA, IndexB = 000
If only Hash then program only IndexB, IndexA = 000
Description
Output Byte Count – up to 2K-1 byte
11’h007-11’h001 not valid (may hang cipher controller)
11’h000 = 0 byte
11’h008 = 8 byte
……
11’h7ff = 2047 bytes
Output byte count must be at least “0” or “8 bytes”.
Input Byte Count - up to 2K-1 byte
11’h007-11’h001 not valid (may hang cipher controller)
11’h000 = 0 byte
11’h008 = 8 bytess
……
11’h7ff = 2047 bytes
Input byte count must be at least “0” or “8 bytes”.
Please note that during Hash calculation, input byte count must be more than equal “8
bytes”
This bit = H, indicates start of a new packet.
This bit = H indicates end of this packet.
When Hash is enable and End_packet is set, this indicates the end for hash algorithm.
this descriptor the ObyteCount[10:0] must be set to the exact # of byte of the authentication
data (for MD5 = 16 byte, for SHA1 = 20 bytes)
Reserved
XOR Mode 1 Select.
This bit = H indicates end of this data type.
type.
Cipher will set these bits when there is an error occurred when process this packet
00 = no error
01 = time out error
10 = error in MD5/SHA1 engine
11 = reserved.
When error occurred, DMA engine will skip the rest of the operation until it see end of
packet.
engines (DES, AES, MD5, SHA1).
If time out occurred, TOINT gets set then interrupt CPU
If error in MD5/SHA1 engine, HAINT gets set then interrupt CPU
Reserved
Description
Reserved
IndexB pointer.
This index uses for Hash engine.
000 = None, do not hash (pass through)
001 = Select Index1 key set
110 = Select Index6 key set
111 = Reserved
Reserved
IndexA pointer.
This index uses for Encryption engine.
000 = None, do not encrypt/decrypt (pass through)
001 = Select Index1 key set
110 = Select Index6 key set
111 = Reserved
……….
……….
0: Normal
1: Select XOR Mode 1.
Before starting process next packet, Cipher controller will issues reset to all
Table 26-18 Control Descriptor
Table 26-19 Index Descriptor
26-10
Next descriptor belongs to different packet.
Next descriptor is belong to the next data
Toshiba RISC Processor
TX4939
In
26
26

Related parts for TX4939XBG-400