TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 71

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

BLOCK
Rev. 3.1 November 1, 2005
Interrupt Controller (IRC)
The Interrupt Controller receives interrupt requests of the on-chip TX4939 peripheral circuits and external
interrupt requests then generates interrupt requests to the TX49/H4 core. Also, the Interrupt Controller has a
16-bit flag register that generates interrupt requests to an external device or to the TX49/H4 core.
□ NMI and 7 external interrupt signal inputs from the on-chip peripheral circuits.
□ Sets 8 priority interrupt levels for each interrupt input.
□ Can select either the edge or the level in the interrupt detection mode for each external interrupt.
□ Has as a flag register for interrupt requests an on-chip 16-bit read/write register. Can issue interrupt requests
On-Chip SRAM
□ 2KB x 1 channel
□ Specifiable base address
□ Accessible by byte, half-word, full-word, or double-words
□ Supports burst access as Cached-Code-Space
□ Supports the critical word first function of the TX49/H4 core
Battery Backup RTC
□ 48-bit liner counter for RTC function
□ Upper 32-bit counts time of second up to 272 years
□ Lower 16-bit represent decimal-place of second
□ 32-bit Alarm register
□ Compare with RTC upper 32-bit all the time
□ Alarm output signal
□ 256Byte internal registers
□ 6 Byte are assigned for data port of RTC and Alarm register
□ 250 Byte are assigned as CMOS RAM
CIPHER Engine
□ Supports DES/3DES/AES
□ Supports MD5/SHA1
□ Dedicated DMA with chain mode
□ Reduced KEY exposure for CBC mode in AES
□ Supports Ex-OR operation
□ Modular Exponentiation Operation Coprocessor Engine
(IRC interrupt) to external devices or to the TX49/H4 core
(a) 6 set of KEY and Initial-data register
(b) KEY registers are W/O (write only)
(c) keep initial data for each stream
(d) Initial data will be updated for CBC mode
(e) Decryption-KEY will be generated from Encryption-KEY without exposure
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Toshiba RISC Processor
TX4939
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