TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 711

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Electrical
27.2.2. Instruction Register
The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting either one or both of the
test to be performed and the Test Data Register to be accessed. The Data Register is selected according to the instruction
code in Table 27-2. Refer to the TX49/H4 Core Architecture Manual for more information regarding each instruction.
Figure 27-1 shows the format of the Instruction Register.
The instruction code is shifted to the Instruction Register starting from the Least Significant Bit.
Rev. 3.1 November 1, 2005
MSB
7
00000100 - 00001111
00010001 - 01111111
10000000 - 11111110
Instruction Code
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
00000011 (0x03)
00010000 (0x10)
11111111 (0xFF)
TDI
MSB → LSB
6
Table 27-2 Bit Configuration of JTAG Instruction Register
Figure 27-2 Shift Direction of the Instruction Register
MSB
5
Figure 27-1 Instruction Register
SAMPLE/PRELOAD
Instruction
Reserved
Reserved
Reserved
BYPASS
EXTEST
IDCODE
HIGHZ
4
Refer to the TX49/H4 Core Architecture Manual
27-3
3
Selected Data Register
LSB
Boundary Scan Register
Boundary Scan Register
Device ID Register
2
Bypass Register
Bypass Register
Reserved
Reserved
Reserved
Toshiba RISC Processor
1
TDO
LSB
0
TX4939
27
27