TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 712
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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Electrical
27.2.3. Boundary Scan Register
The Boundary Scan Register contains a single 256-bit shift register to which all TX4939 I/O signals except for power supply,
TDI, TCK, TDO, TMS, TRST*, and TEST[4]* are connected. Figure 27-3 shows the bits of the Boundary Scan Register.
TDI input is fetched to the Least Significant Bit (LSB) of the Boundary Scan Register and the Most Significant Bit (MSB) of
the Boundary Scan Register is sent from the TDO output.
27.2.4. Device ID Register
The Device ID Register is a 32-bit shift register. This register is used for reading the ID code that expresses the IC
manufacturer, part number, and version from the IC and sending it to a serial device. The following figure shows the
configuration of the Device ID Register.
The device ID code for the TX4939 is 0x2003_7031. However, the four top bits of the Version field may be changed. The
device ID code is shifted out from the Least Significant Bit.
27.2.5. Initializing the Extended EJTAG Interface
The Extended EJTAG Interface is not reset by asserting the RESET* signal. Operation of the TX49/H4 core is not
guaranteed if the Extended EJTAG Interface is not reset. This interface is initialized by either of the following methods.
Rev. 3.1 November 1, 2005
31
0
Version
0
4 bits
Assert the TRST* signal.
After clearing the processor reset, set the TMS input to High for five consecutive rising edges of the TCK input.
The reset state is maintained if TMS is able to maintain the High state.
The above methods must be performed while the MASTERCLK signal is being input. Also, externally fix the
TRST* signal to GND when not using an emulation probe. The G-Bus Time Out Detection function is disabled
when the TRST* signal is deasserted.
1
28
0
255
27
0
0
0
0
MSB
Figure 27-5 Shift Direction of the Device ID Register
0
0
Product Number
Figure 27-3 Boundary Scan Register
0
16 bits
Figure 27-4 Device ID Register
0
Refer to TX4939 BSDL file
0
……
0
1
27-4
1
0
1
1
LSB
12 11
1
0
0
0
Manufacturer ID Code
0
TDO
Toshiba RISC Processor
0
11 bits
0
1
1
0
0
0
TX4939
0
1
0
1
1
27
27
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