TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 713

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Electrical
27.2.6. Features
27.2.7. EJTAG interface
This interface consists of two modes of operation a Run Time Mode and Real Time Mode. The Run Time Mode provides
functions such as processor Run, STOP, Single Step, and access to internal registers and system memory. The Real Time
mode provides additional status pins used in conjunction with JTAG pins for Real Time Trace information.
Rev. 3.1 November 1, 2005
PIN NAME
JTDI
JTCK
JTDO/TPC(0)
JTMS
DCLK
PCST(8:0)
TPC(3:1) Note 1
TRST *
Note1: Leave TPC (3-1) pins open when not using them as PC trace outputs for debugging.
1.
2.
3.
4.
5.
6.
Utilizes JTAG interface compatible with IEEE Std. 1149.1.
Processor access to external processor probe to execute from the external trace memory during
debug exception and boot time. This is to eliminate system memory for debugging purpose.
Supports DMA access through JTAG interface to internal processor bus to access internal
registers, host system peripherals and system memory.
Debug functions
Instructions for Debug
CP0 Registers for Debug
Instruction Address Break
Data Bus break
Processor Bus Break
Reset, NMI, Interrupt Mask
SDBBP, DERET, CTC0, CFC0
Debug, DEPC, DESAVE
I / O
I
I
O
I
O
O
O
I
FUNCTION
JTAG data input / Debug interrupt input
Run-time mode: Input serial data to JTAG data/instruction registers.
Real-time mode: Interrupt input to change the debug unit state from real-time mode to run-time
mode.
JTAG clock input
Clock input for JTAG. The JTDI and JTMS data are latched on rising edges of this clock.
JTAG data output / Trace PC output
Data is serially shifted out from this pin. / Outputs a non-sequential program counter value
synchronously with DCLK.
JTAG command
Controls mainly the status transition of the TAP controller state machine.
When the serial input data is a JTAG command, apply a high signal (= 1) to this pin.
Debug clock (1/3 CPU clock)
Clock output for a real-time debug system. Timings of the serial monitor bus and PC trace interface
signals all are defined by this debug clock DCLK.
This Debug clock frequency is 1/3 that of CPUCLK.
PC trace status
Outputs PC trace status information and serial monitor bus mode.
Trace PC output
Outputs a non-sequential program counter value synchronously with DCLK.
Test reset input
Reset input for a real-time debug system. When TRST* is asserted (= 0), the debug support unit
(DSU) is initialized.
Table 27-3 JTAG Interface
27-5
Toshiba RISC Processor
TX4939
27
27

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