TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 731

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Electrical
28.4.8. AC characteristics of ATA Interface
28.4.8.1. Register transfers to/from device
Rev. 3.1 November 1, 2005
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0
1
2
2i
3
4
5
6
6z
9
RD
A
B
C
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
Register transfer timing parameters
DESCRIPTION
SRISE
SFALL
Chost
Cdevice
NOTE :
Cycle time
Address valid to DIOR-/DIOW-
Setup
DIOR-/DIOW- pulse width 8-bit
DIOR-/DIOW- recovery time
DIOW- data setup
DIOW- data hold
DIOR- data setup
DIOR- data hold
DIOR- data tristate
DIOR-/DIOW- to address valid
Hold
Read Data Valid to IORDY active (min)
(if IORDY initially low after tA)
IORDY Setup time
IORDY Pulse Width
IORDY Pulse Width
t
minimum DIOR-/DIOW- negation time. A host implementation shall lengthen t
t
implementation shall support any legal host implementation.
This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is
released by the device.
The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If
the device is not driving IORDY negated at the t
be met and t
of DIOR- or DIOW-, then t
ATA/ATAPI standards prior to ATA/ATAPI-5 inadvertently specified an incorrect value for mode 2 time t
by utilizing the 16-bit PIO value
Mode shall be selected no faster than the highest mode supported by the slowest device.
0
0
is the minimum total cycle time, t
is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device
connector from 10-90% of full signal amplitude with all capacitive loads from 15 pf
through 40 pf where all signals have the same capacitive load value.
SRISE and SFALL shall meet this requirement when measured at the sender’s
RD
Rising edge slew rate for any signal on AT interface (see note)
Falling edge slew rate for any signal on AT interface
(see note)
Host interface signal capacitance at the host connector
Device interface signal capacitance at the device
Connector
is not applicable. If the device is driving IORDY negated at the time t
(min)
RD
(min)
(min)
(min)
(max)
(min)
(max)
(max)
shall be met and t
(min)
(min)
(min)
(min)
2
is the minimum DIOR-/DIOW- assertion time, and t
28-15
Mode 0
1250
600
290
ns
70
60
30
50
30
20
35
5
0
5
-
5
A
is not applicable.
after the activation of DIOR- or DIOW-, then t
Mode 1
1250
383
290
ns
50
45
20
35
30
15
35
5
0
5
-
Mode 2
1250
330
290
ns
30
30
15
20
30
10
35
5
0
5
-
Toshiba RISC Processor
Mode 3
1250
MIN
180
ns
2
30
80
70
30
10
20
30
10
35
5
0
5
and/or t
A
after the activation
Mode 4
MAX
2i
1250
25 pf
20 pf
120
1.25
V/ns
1.25
V/ns
ns
25
70
25
20
10
20
30
10
35
to ensure that
5
0
5
2i
is the
1,4,5
1
1
2
3
Note
5
TX4939
shall
0
28
28