TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 734

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
Electrical
28.4.8.3. Ultra DMA data burst timing requirements
Rev. 3.1 November 1, 2005
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTE 1 Timing parameters shall be measured at the connector of the sender or receiver to which the parameter
NOTE 2 All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.
NOTE 3 t
NOTE 4 The test load for t
NOTE 5 t
2CYCTYP
CYC
2CYC
DS
DH
DVS
DVH
FS
LI
MLI
UI
AZ
ZAH
ZAD
ENV
SR
RFS
RP
IORDYZ
ZIORDY
ACK
SS
Name
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
applies. For example, the sender shall stop generating STROBE edges t
Both STROBE and
DMARDY- timing measurements are taken at the connector of the sender.
waiting for the other to respond with a signal before proceeding. t
maximum time value.
t
and t
load value.
released.
min max min max min max min max min max
UI
MLI
ZIORDY
240
230
160
112
15
70
20
20
20
20
50
Mode 0
5
6
0
0
0
0
0
, t
(ns)
is a limited time-out that has a defined minimum. t
MLI
DVH
may be greater than t
230
150
, and t
10
70
50
75
20
shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive
160
154
125
73
20
20
20
50
LI
10
48
20
Mode 1
5
6
0
0
0
0
0
indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is
(ns)
DVS
200
150
10
70
30
70
20
and t
120
100
115
DVH
54
30
20
20
20
20
50
Mode 2
7
5
6
0
0
0
0
0
ENV
(ns)
shall be a lumped capacitor load with no cable or receivers. Timing for t
since the device has a pull up on IORDY- giving it a known state when
170
150
10
70
20
60
20
100
90
39
86
20
20
20
20
20
50
Mode 3
7
5
6
0
0
0
0
0
(ns)
28-18
130
100
NA
10
55
60
20
100
60
25
57
20
20
20
20
50
Mode 4
5
5
6
6
0
0
0
0
0
LI
(ns)
is a limited time-out that has a defined maximum.
120
100
NA
10
55
60
20
Typical sustained average two cycle time
Cycle time allowing for asymmetry and clock
variations (from STROBE edge to STROBE edge)
Two cycle time allowing for clock variations (from
rising edge to next rising edge or from falling edge
to next falling edge of STROBE)
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender (from data valid until
STROBE edge) (see Note 4)
Data valid hold time at sender (from STROBE edge
until data may become invalid) (see Note 4)
First STROBE time (for device to first negate
DSTROBE from STOP during a data in burst)
Limited interlock time (see Note 3)
Interlock time with minimum (see Note 3)
Unlimited interlock time (see Note 3)
Maximum time allowed for output drivers to release
(from asserted or negated)
Minimum delay time required for output
drivers to assert or negate (from released)
Envelope time (from DMACK- to STOP and
HDMARDY- during data in burst initiation and from
DMACK to STOP during data out burst initiation)
STROBE-to-DMARDY- time (if DMARDY- is
negated before this long after STROBE edge, the
recipient shall receive no more than one additional
data word)
Ready-to-final-STROBE time (no STROBE edges
shall be sent this long after negation of DMARDY-)
Minimum time to assert STOP or negate DMARQ.
Maximum time before releasing IORDY
Minimum time before driving STROBE
(see note 5)
Setup and hold times for DMACK- (before assertion
or negation)
Time from STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a
burst)
UI
is an unlimited interlock that has no
RFS
(see Notes 1 and 2)
after the negation of DMARDY-.
Toshiba RISC Processor
Comment
TX4939
DVS
28
28

Related parts for TX4939XBG-400