TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 76

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Pin Assignment
3.2. Pin Alignment (TOP VIEW)
Rev. 3.1 November 1, 2005
AA
AB
AC
AD
AE
AF
C
D
G
M
W
A
B
E
F
H
K
N
P
R
U
V
0
J
L
T
Y
PCICLK
PCICLK
PCICLK
PCICLK
PCICLK
DEVSE
REQ1* PCIRST GNT2* REQ2* VDD33
PCIAD
PCIAD
PCIAD
PCIAD
PCIAD
SERR* PAR CBE1*
PCIAD
PCIAD
PCIAD
PCIAD
PCIAD
VSS
VSS
BE1* SA00 VSS SA03 SA02
CE2*
INT2* INT1* INT0* CE1*
PME* REQ0* GNT0* GNT1* VDDC
VSS
VSS
29
25
24
21
18
14
11
08
05
02
1
IN
L*
1
2
3
4
FRAME
REQ4* GNT5* REQ5* VDDC
GNT3* REQ3* GNT4* VDD33
PCIAD
CBE3*
PCIAD
STOP* LOCK* PERR* VDD33
PCIAD
CBE0*
PCIAD
PCIAD
INTB* INTA* NMI* VDD33
VSS SA04
VSS SA01
CE3*
VSS INTD* INTC* VDDC
VSS
VSS
VSS
VSS
VSS
26
17
10
04
01
2
*
A0_DA
M66EN
PCIAD
PCIAD
PCIAD
PCIAD
PCIAD
IRDY* TRDY* VDD33
PCIAD
PCIAD
PCIAD
PCIAD
BE0*
VSS
SP*
30
27
23
20
16
13
07
03
00
3
A0_DC
A0_DC
A0_DA
DMAR
DMAA
PCIAD
PCIAD
PCIAD
PCIAD
CBE2* VDDC
PCIAD
PCIAD
PCIAD
PCIAD
EQ1
VSS SA05
VSS
CK1
S1*
S0*
31
28
22
19
15
12
09
06
4
2
VDD33
VDD33
VDD33
A0_DA
A0_PDI
A0_DA
DMAR
DMAA
VDDC
VDDC
VDDC
VDDC
A0_DI
EQ2
VSS VDD33 VDDC VDDC VDD33 VDD33 VDDC VDDC VDD33 VDD33 VDDC VDDC VDD33 VDD33 VDDC VDDC VDD33 VSS
VSS VDD33 VDDC VDDC VDD33 VDD33 VDDC VDDC VDD33 VDD33 VDDC VDDC VDD33 VDD33 VDDC VDDC VDD33 VSS
CK2
AG*
NTR
5
0
1
Package Outl i ne TX4939XBG
A0_DM
DMAA
DMAR
ORDY
SWE* VSS
A0_DI
A0_DI
A0_DI
ACK*
EQ0
OW*
OE*
CK0
OR*
6
SADB1
SADB1
SADB1
A0_DM
A0_DD
A0_DD
AREQ
VSS
15
00
7
3
4
5
Figure 3-1 Pin Assignment on Package (TOP VIEW)
SADB1
SADB1
SADB1
A0_DD
A0_DD
A0_DD
A0_DD
ACE*
14
01
13
02
8
0
1
2
SYSCL
SADB0
SADB0
SADB0
A0_DD
A0_DD
A0_DD
A0_DD
12
03
11
04
9
K
7
8
9
SADB0
SADB0
SADB0
SADB0
A0_DD
A0_DD
A0_DD
A0_DD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
10
05
09
06
3
4
5
6
SADB0
SADB0
SADB0
A0_DD
A0_DD
A0_DR
A1_DA
ACK*
VSS
VSS
VSS
VSS
VSS
VSS
ST*
SP*
08
07
0
1
2
NDRB* TIMER1 TIMER0 GP00
A1_DC
A1_DC
A1_DA
NRCE* NDCE* GP02 SPICLK
DMAD
ONE*
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S1*
S0*
2
3-4
A1_DA
A1_PDI
A1_DA
WDRS
NDLA GP01 SPICS0 EJRST* SDIN1 TXD1 VDDR TXD0
A1_DI
VSS
VSS
VSS
VSS
VSS
VSS
AG*
NTR
T*
0
1
A1_DM
ORDY
A1_DI
A1_DI
A1_DI
GP03
ACK*
VSS
VSS
VSS
VSS
VSS
VSS
OW*
OR*
A1_DD
A1_DD
A1_DM
AREQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
00
15
A1_DD
A1_DD
A1_DD
A1_DD
SPIOU
I2C_D
SPIIN BITCLK SYNC
VSS
VSS
VSS
VSS
VSS
VSS
02
13
01
14
O
T
I2C_CL
A1_DD
A1_DD
A1_DD
A1_DD
SDIN0
04
11
03
12
K
SDOUT X32IN
ACRES
A1_DD
A1_DD
A1_DD
A1_DD
ET*
06
09
05
10
X32OU
RTCVD
VDCLK
A1_DR
A1_DD
A1_DD
ST*
IN1
07
08
T
D
Toshiba RISC Processor
VDPSN
VDCLK
ALAR
VDVL
RXD1
VSS
VSS
D1
O1
M*
1
VDCLK
VDCLK
SSPLL
BYPA
VDVL
VDS1 VDPSN VD3
RXD0 TRST* TDO
TMS
TDI
IN
D
O
HALTD
TEST0* VSS
VDD25 VSS
VDD25
VDD25
VDD25
VDD25 DRBA1 DRA10 DRA13
VDD25 DRA8 DRA9 DRA6 DRA7
VDD25 VSS DRCKE DRA12 DRA11
VDD25 DRDQ7 DRDQ8 DRDQ9
VDDC VSS
VDDC
VDDC
VDDC
VDDC DRA0
VDDC DRA4 DRA5 DRA2 DRA3
VDDC
VDDC
TCK
OZE
VD2
VD1
VD0
TOPVI EW
div_RS
MSTCL
DRDQ2
DRDQ2
DRDQ2
DRDQ1
DRCS1
DRDQ1
DRDQ1
DRDQ
DRDQ
VSS
VSS DRDQ2 DRDQ3 DRDM0
VD5
VD4
K2
S2
S0
T*
9
7
3
7
*
2
1
MSTCL
DRCKR
DRDQ3
DRDQ2
DRDQ2
DRDQ2
DRDM2
DRDQ1
DRWE*
DRDQ1
DRDM1 VSS
DRDQ4 DRDQ5 DRDQ6
RESET
DRVre
PLL12
VDD_
DRCK
VSS
OUT
VSS DRDQ0 DRDQ1
VD7
VD6
EF
f1
K
*
1
8
6
2
6
3
TX4939
DRDQ2
DRDQ2
DRDQ1
DRDQ1
PLL3V
DD_A
PLL12
VSS_
DRDQ
DRCA
VSS
VSS
VSS
VSS DRCKP
VSS
VSS
VSS DRA1
VSS
VSS
S3
S*
5
1
9
4
DRDQ3
DRDM3
DRDQ2
DRDQ2
DRDQ1
DRCS0
DRBA0
DRDQ1
DRDQ1
PLL3V
SS_A
DRCK
DRRA
DRDQ
VSS
VSS
VSS
VSS
VSS
S1
S*
M
0
4
0
8
*
5
0
3
3