TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 80

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Pin Assignment
3.3.8. Default GPIO
3.3.9. PCI Interface Signals
Rev. 3.1 November 1, 2005
Note: With the PCI Host mode, both external and internal arbiter can be used. But the PCI Satellite mode,
Default GPIO Signals
Signal Name
GPIO00
GPIO01
GPIO02
GPIO03
PCI Interface
Signal Name
Signals for Host Mode
PCICLK[4:1]
PCIRST
PCICLKIN
PCIAD[31:0]
C_BE[3:0]*
PAR
FRAME*
IRDY*
TRDY*
STOP*
LOCK*
DEVSEL*
REQ[5:1]*
REQ[0]*
GNT[0]*
GNT[5:1]*
PERR*
SERR*
M66EN
PME*
Additional Signals for External Arbiter and Satellite Mode (Note)
REQ*
GNT*
INTOUT*
IDSEL
only external arbiter mode available.
I/O
I/O
Output
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Output
Input
Output
Input
I/O
I/O
I/O
I/O
I/O
System Error
Power Management
Function
Default GPIO 00
Default GPIO 01
Default GPIO 02
Default GPIO 03
Function
PCI Clock (Service Clock)
These are the service PCI Clocks.
PCI Bus Reset Signal (Service Output)
Reset Output for PCI Bus target cards.
PCI Clock Input
This is the PCI Clock input.
PCI Address and Data
This is the Address/Data Multiplex Bus.
Command and Byte Enable
This is the Command and Byte Enable signal.
Parity
This is the Parity signal for PCIAD[31:0] and C_BE[3:0]*. Parity is even.
Cycle Frame
Indicates that a bus operation is being run.
Initiator Ready
This signal indicates that the Initiator has finished transferring data.
Target Ready
This signal indicates that the Target is ready to finish transferring data.
Stop
This signal indicates that the Target requests the Initiator to stop transferring data.
PCI Resource Clock
This signal indicates that the PCI Bus Master has locked (established exclusive access
to) a particular memory Target on the PCI Bus.
Device Select
The Target asserts this response signal to access performed by the Initiator.
Request
The PCI Arbiter’s Bus Request inputs for the channel of 1 to 5.
Request
In the internal arbiter mode this pin will be 6
Grant
In the internal arbiter mode this pin will be 6
Grant
The PCI Arbiter’s Bus Grant Output for the channel of 1 to 5
Data Parity Error
This signal indicates that a data parity error occurred in a bus cycle other than a Special
cycle.
This signal indicates that either an address parity error, a data parity error during a
Special cycle, or a fatal error occurred.
66 MHz Clock Enable
1: Enable the 66 MHz operation mode.
0: Disable the 66 MHz operation mode.
This signal indicates the Power Management mode status.
This pin represents REQ* output signal of internal PCI core.
This pin represents GNT* input of internal PCI Core.
Extra Interrupt output.
This pin represents IDSEL input for Satellite mode.
3-8
th
th
arbiter REQ* input.
arbiter GNT* output.
Toshiba RISC Processor
TX4939
3
3