TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 89

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
Pin Assignment
3.4.6. Pin Multiplexing for ISA
ISA interface signals are sharing with NOR/NAND/RAM interface (EBC interface). Table 3-10 is the list all of signals that
are used in ISA mode. Figure 9-1 in chapter 9 shows how ISA connects to EBC interface signals.
At the Boot time
After Boot up, if the system has ISA connector on board then firmware must enable ISA mode for that channel by program
to EBCCRn register bit 22. See Chapter 9 for more information
Note: Both DMAREQ[2] and DMAAC[2] used Pull-Up IO pad.
3.4.7. Pin Multiplexing for PCICLK [4:1]
Rev. 3.1 November 1, 2005
Default Signal Name BOOT Default
PCICLK[4]
PCICLK[3]
PCICLK[2]
PCICLK[1]
-
-
DMAREQ[2] are default to be input mode. The state of DMAREQ[2] is HIGH since there is Pull-Up on the
internal IO pad.
DMAACK[2] are default to be output mode. The state of DMAACK[2] is HIGH after RESET.
Default Signal Name
DMAREQ[2]
DMAACK[2]
BE[1]
ACK*/READY
SADB[15:0]
SA[5:0]
BE[0]
IOSRST*
SYSRST*
(PCICLK Stopped)
(PCICLK Running)
Table 3-11 PCICLK signal multiplexing
Table 3-10 ISA Signal Multiplexing
PCICLK ON
PCICLK
PCICLK
PCICLK
PCICLK
ISA
IOR*
IOW*
BHE*
WAIT
DATA[15:0]
SA[6:1]
SA[0]
3-17
COMMENT
PCICLK is OFF and IOSRST* will be assert during
RESET* assertion.
During PCICLK[4] is ON, IOSRST function will be
disengaged
PCICLK is OFF and SYSRST* will be deassert by
RESET* assertion.
During PCICLK[3] is ON, SYSRST function will be
disengaged
PCICLK is OFF at boot time
PCICLK is ON at boot time
Ball Name
A5
B5
C1
D11
A11,B11,C11,A10,B10
,C10,D10,B9,C9,D9,
B8,C8,D8,A7,C7,D7
C2,B3,C5,C4,A3,D5
D3
Toshiba RISC Processor
TX4939
3
3

Related parts for TX4939XBG-400